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riscv-gcc-1
Commit 50fe8924 by Oleg Endo
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divtab.c: Fix formatting and comments throughout the file. 

	* config/sh/divtab.c: Fix formatting and comments throughout the file.
	* config/sh/sh4-300.md: Likewise.
	* config/sh/sh4a.md: Likewise.
	* config/sh/constraints.md: Likewise.
	* config/sh/sh.md: Likewise.
	* config/sh/netbsd-elf.h: Likewise.
	* config/sh/predicates.md: Likewise.
	* config/sh/sh-protos.h: Likewise.
	* config/sh/ushmedia.h: Likewise.
	* config/sh/linux.h: Likewise.
	* config/sh/sh.c: Likewise.
	* config/sh/superh.h: Likewise.
	* config/sh/elf.h: Likewise.
	* config/sh/sh4.md: Likewise.
	* config/sh/sh.h: Likewise.

From-SVN: r195703
parent 1a04ac2b
Showing with 690 additions and 850 deletions
gcc/ChangeLog
2013-02-03 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/divtab.c: Fix formatting and comments throughout the file.
* config/sh/sh4-300.md: Likewise.
* config/sh/sh4a.md: Likewise.
* config/sh/constraints.md: Likewise.
* config/sh/sh.md: Likewise.
* config/sh/netbsd-elf.h: Likewise.
* config/sh/predicates.md: Likewise.
* config/sh/sh-protos.h: Likewise.
* config/sh/ushmedia.h: Likewise.
* config/sh/linux.h: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/superh.h: Likewise.
* config/sh/elf.h: Likewise.
* config/sh/sh4.md: Likewise.
* config/sh/sh.h: Likewise.
2013-02-03 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2013-02-03 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* config/pa/constraints.md: Adjust unused letters. Change "T" * config/pa/constraints.md: Adjust unused letters. Change "T"
......
gcc/config/sh/constraints.md
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
;; Csu: unsigned 16-bit constant, literal or symbolic ;; Csu: unsigned 16-bit constant, literal or symbolic
;; Csy: label or symbol ;; Csy: label or symbol
;; Cpg: non-explicit constants that can be directly loaded into a general ;; Cpg: non-explicit constants that can be directly loaded into a general
;; purpose register in PIC code. like 's' except we don't allow ;; purpose register in PIC code. Like 's' except we don't allow
;; PIC_ADDR_P ;; PIC_ADDR_P
;; IJKLMNOP: CONT_INT constants ;; IJKLMNOP: CONT_INT constants
;; Ixx: signed xx bit ;; Ixx: signed xx bit
...@@ -315,7 +315,7 @@ ...@@ -315,7 +315,7 @@
(match_test "satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))"))) (match_test "satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))")))
(define_memory_constraint "Sra" (define_memory_constraint "Sra"
"A memory reference that uses a simple register addressing." "A memory reference that uses simple register addressing."
(and (match_test "MEM_P (op)") (and (match_test "MEM_P (op)")
(match_test "REG_P (XEXP (op, 0))"))) (match_test "REG_P (XEXP (op, 0))")))
gcc/config/sh/divtab.c
...@@ -53,7 +53,8 @@ double max_defect3 = 0.; ...@@ -53,7 +53,8 @@ double max_defect3 = 0.;
double max_defect3_x; double max_defect3_x;
int max_defect3_val; int max_defect3_val;
static double note_defect3 (int val, double d2, double y2d, double x) static double
note_defect3 (int val, double d2, double y2d, double x)
{ {
int cutoff_val = val >> CUTOFF_BITS; int cutoff_val = val >> CUTOFF_BITS;
double cutoff; double cutoff;
...@@ -172,8 +173,10 @@ main () ...@@ -172,8 +173,10 @@ main ()
printf (" Min defect: %e at %e\n", min_defect, min_defect_x); printf (" Min defect: %e at %e\n", min_defect, min_defect_x);
printf (" Max 2nd step defect: %e at %e\n", max_defect2, max_defect2_x); printf (" Max 2nd step defect: %e at %e\n", max_defect2, max_defect2_x);
printf (" Min 2nd step defect: %e at %e\n", min_defect2, min_defect2_x); printf (" Min 2nd step defect: %e at %e\n", min_defect2, min_defect2_x);
printf (" Max div defect: %e at %d:%e\n", max_defect3, max_defect3_val, max_defect3_x); printf (" Max div defect: %e at %d:%e\n", max_defect3, max_defect3_val,
printf (" Min div defect: %e at %d:%e\n", min_defect3, min_defect3_val, min_defect3_x); max_defect3_x);
printf (" Min div defect: %e at %d:%e\n", min_defect3, min_defect3_val,
min_defect3_x);
printf (" Defect at 1: %e\n", printf (" Defect at 1: %e\n",
calc_defect (1., constants[0], factors[0])); calc_defect (1., constants[0], factors[0]));
printf (" Defect at -2: %e */\n", printf (" Defect at -2: %e */\n",
......
gcc/config/sh/elf.h
...@@ -22,17 +22,17 @@ along with GCC; see the file COPYING3. If not see ...@@ -22,17 +22,17 @@ along with GCC; see the file COPYING3. If not see
#undef TARGET_ELF #undef TARGET_ELF
#define TARGET_ELF 1 #define TARGET_ELF 1
/* Generate DWARF2 debugging information and make it the default */ /* Generate DWARF2 debugging information and make it the default. */
#define DWARF2_DEBUGGING_INFO 1 #define DWARF2_DEBUGGING_INFO 1
#undef PREFERRED_DEBUGGING_TYPE #undef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
/* use a more compact format for line information */ /* Use a more compact format for line information. */
#define DWARF2_ASM_LINE_DEBUG_INFO 1 #define DWARF2_ASM_LINE_DEBUG_INFO 1
#undef WCHAR_TYPE #undef WCHAR_TYPE
/* #define WCHAR_TYPE (TARGET_SH5 ? "int" : "long int") */ /* #define WCHAR_TYPE (TARGET_SH5 ? "int" : "long int") */
#define WCHAR_TYPE SH_ELF_WCHAR_TYPE #define WCHAR_TYPE SH_ELF_WCHAR_TYPE
#undef WCHAR_TYPE_SIZE #undef WCHAR_TYPE_SIZE
...@@ -40,7 +40,6 @@ along with GCC; see the file COPYING3. If not see ...@@ -40,7 +40,6 @@ along with GCC; see the file COPYING3. If not see
/* The prefix to add to user-visible assembler symbols. */ /* The prefix to add to user-visible assembler symbols. */
#undef LOCAL_LABEL_PREFIX #undef LOCAL_LABEL_PREFIX
#define LOCAL_LABEL_PREFIX "." #define LOCAL_LABEL_PREFIX "."
......
gcc/config/sh/linux.h
...@@ -57,7 +57,6 @@ along with GCC; see the file COPYING3. If not see ...@@ -57,7 +57,6 @@ along with GCC; see the file COPYING3. If not see
%{static:-static}" %{static:-static}"
/* Output assembler code to STREAM to call the profiler. */ /* Output assembler code to STREAM to call the profiler. */
#undef FUNCTION_PROFILER #undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(STREAM,LABELNO) \ #define FUNCTION_PROFILER(STREAM,LABELNO) \
do { \ do { \
......
gcc/config/sh/netbsd-elf.h
...@@ -41,7 +41,6 @@ along with GCC; see the file COPYING3. If not see ...@@ -41,7 +41,6 @@ along with GCC; see the file COPYING3. If not see
NetBSD ELF LINK_SPEC. */ NetBSD ELF LINK_SPEC. */
/* LINK_EMUL_PREFIX from sh/elf.h */ /* LINK_EMUL_PREFIX from sh/elf.h */
#undef SUBTARGET_LINK_EMUL_SUFFIX #undef SUBTARGET_LINK_EMUL_SUFFIX
#define SUBTARGET_LINK_EMUL_SUFFIX "_nbsd" #define SUBTARGET_LINK_EMUL_SUFFIX "_nbsd"
......
gcc/config/sh/predicates.md
...@@ -18,7 +18,6 @@ ...@@ -18,7 +18,6 @@
;; <http://www.gnu.org/licenses/>. ;; <http://www.gnu.org/licenses/>.
;; TODO: Add a comment here. ;; TODO: Add a comment here.
(define_predicate "trapping_target_operand" (define_predicate "trapping_target_operand"
(match_code "if_then_else") (match_code "if_then_else")
{ {
...@@ -58,8 +57,7 @@ ...@@ -58,8 +57,7 @@
&& INTVAL (XEXP (cond, 1)) == 3); && INTVAL (XEXP (cond, 1)) == 3);
}) })
;; TODO: Add a comment here. ;; A logical operand that can be used in an shmedia and insn.
(define_predicate "and_operand" (define_predicate "and_operand"
(match_code "subreg,reg,const_int") (match_code "subreg,reg,const_int")
{ {
...@@ -77,7 +75,6 @@ ...@@ -77,7 +75,6 @@
;; Like arith_reg_dest, but this predicate is defined with ;; Like arith_reg_dest, but this predicate is defined with
;; define_special_predicate, not define_predicate. ;; define_special_predicate, not define_predicate.
(define_special_predicate "any_arith_reg_dest" (define_special_predicate "any_arith_reg_dest"
(match_code "subreg,reg") (match_code "subreg,reg")
{ {
...@@ -86,7 +83,6 @@ ...@@ -86,7 +83,6 @@
;; Like register_operand, but this predicate is defined with ;; Like register_operand, but this predicate is defined with
;; define_special_predicate, not define_predicate. ;; define_special_predicate, not define_predicate.
(define_special_predicate "any_register_operand" (define_special_predicate "any_register_operand"
(match_code "subreg,reg") (match_code "subreg,reg")
{ {
...@@ -94,7 +90,6 @@ ...@@ -94,7 +90,6 @@
}) })
;; Returns 1 if OP is a valid source operand for an arithmetic insn. ;; Returns 1 if OP is a valid source operand for an arithmetic insn.
(define_predicate "arith_operand" (define_predicate "arith_operand"
(match_code "subreg,reg,const_int,truncate") (match_code "subreg,reg,const_int,truncate")
{ {
...@@ -132,7 +127,6 @@ ...@@ -132,7 +127,6 @@
;; Like above, but for DImode destinations: forbid paradoxical DImode ;; Like above, but for DImode destinations: forbid paradoxical DImode
;; subregs, because this would lead to missing sign extensions when ;; subregs, because this would lead to missing sign extensions when
;; truncating from DImode to SImode. ;; truncating from DImode to SImode.
(define_predicate "arith_reg_dest" (define_predicate "arith_reg_dest"
(match_code "subreg,reg") (match_code "subreg,reg")
{ {
...@@ -144,7 +138,6 @@ ...@@ -144,7 +138,6 @@
}) })
;; Returns 1 if OP is a normal arithmetic register. ;; Returns 1 if OP is a normal arithmetic register.
(define_predicate "arith_reg_operand" (define_predicate "arith_reg_operand"
(match_code "subreg,reg,sign_extend") (match_code "subreg,reg,sign_extend")
{ {
...@@ -190,7 +183,6 @@ ...@@ -190,7 +183,6 @@
}) })
;; Returns 1 if OP is a valid source operand for a compare insn. ;; Returns 1 if OP is a valid source operand for a compare insn.
(define_predicate "arith_reg_or_0_operand" (define_predicate "arith_reg_or_0_operand"
(match_code "subreg,reg,const_int,const_vector") (match_code "subreg,reg,const_int,const_vector")
{ {
...@@ -203,21 +195,18 @@ ...@@ -203,21 +195,18 @@
return 0; return 0;
}) })
;; TODO: Add a comment here. ;; Returns 1 if OP is a floating point operator with two operands.
(define_predicate "binary_float_operator" (define_predicate "binary_float_operator"
(and (match_code "plus,minus,mult,div") (and (match_code "plus,minus,mult,div")
(match_test "GET_MODE (op) == mode"))) (match_test "GET_MODE (op) == mode")))
;; TODO: Add a comment here. ;; Returns 1 if OP is a logical operator with two operands.
(define_predicate "binary_logical_operator" (define_predicate "binary_logical_operator"
(and (match_code "and,ior,xor") (and (match_code "and,ior,xor")
(match_test "GET_MODE (op) == mode"))) (match_test "GET_MODE (op) == mode")))
;; Return 1 of OP is an address suitable for a cache manipulation operation. ;; Return 1 if OP is an address suitable for a cache manipulation operation.
;; MODE has the meaning as in address_operand. ;; MODE has the meaning as in address_operand.
(define_special_predicate "cache_address_operand" (define_special_predicate "cache_address_operand"
(match_code "plus,reg") (match_code "plus,reg")
{ {
...@@ -234,8 +223,7 @@ ...@@ -234,8 +223,7 @@
return address_operand (op, mode); return address_operand (op, mode);
}) })
;; Return 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu. ;; Returns 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
(define_predicate "cmp_operand" (define_predicate "cmp_operand"
(match_code "subreg,reg,const_int") (match_code "subreg,reg,const_int")
{ {
...@@ -248,8 +236,8 @@ ...@@ -248,8 +236,8 @@
return arith_reg_operand (op, mode); return arith_reg_operand (op, mode);
}) })
;; TODO: Add a comment here. ;; Returns true if OP is an operand that can be used as the first operand in
;; the cstoresi4 expander pattern.
(define_predicate "cmpsi_operand" (define_predicate "cmpsi_operand"
(match_code "subreg,reg,const_int") (match_code "subreg,reg,const_int")
{ {
...@@ -260,19 +248,18 @@ ...@@ -260,19 +248,18 @@
return arith_operand (op, mode); return arith_operand (op, mode);
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a comutative float operator.
;; This predicate is currently unused.
(define_predicate "commutative_float_operator" ;;(define_predicate "commutative_float_operator"
(and (match_code "plus,mult") ;; (and (match_code "plus,mult")
(match_test "GET_MODE (op) == mode"))) ;; (match_test "GET_MODE (op) == mode")))
;; TODO: Add a comment here.
;; Returns true if OP is a equal or not equal operator.
(define_predicate "equality_comparison_operator" (define_predicate "equality_comparison_operator"
(match_code "eq,ne")) (match_code "eq,ne"))
;; TODO: Add a comment here. ;; Returns true if OP is an arithmetic operand that is zero extended during
;; an operation.
(define_predicate "extend_reg_operand" (define_predicate "extend_reg_operand"
(match_code "subreg,reg,truncate") (match_code "subreg,reg,truncate")
{ {
...@@ -281,8 +268,7 @@ ...@@ -281,8 +268,7 @@
: arith_reg_operand) (op, mode); : arith_reg_operand) (op, mode);
}) })
;; TODO: Add a comment here. ;; Like extend_reg_operand, but also allow a constant 0.
(define_predicate "extend_reg_or_0_operand" (define_predicate "extend_reg_or_0_operand"
(match_code "subreg,reg,truncate,const_int") (match_code "subreg,reg,truncate,const_int")
{ {
...@@ -292,15 +278,14 @@ ...@@ -292,15 +278,14 @@
}) })
;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND. ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
(define_predicate "ext_dest_operand" (define_predicate "ext_dest_operand"
(match_code "subreg,reg") (match_code "subreg,reg")
{ {
return arith_reg_operand (op, mode); return arith_reg_operand (op, mode);
}) })
;; TODO: Add a comment here. ;; Returns true if OP can be used as a destination register for shmedia floating
;; point to integer conversions.
(define_predicate "fp_arith_reg_dest" (define_predicate "fp_arith_reg_dest"
(match_code "subreg,reg") (match_code "subreg,reg")
{ {
...@@ -310,8 +295,8 @@ ...@@ -310,8 +295,8 @@
return fp_arith_reg_operand (op, mode); return fp_arith_reg_operand (op, mode);
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a floating point register that can be used in floating
;; point arithmetic operations.
(define_predicate "fp_arith_reg_operand" (define_predicate "fp_arith_reg_operand"
(match_code "subreg,reg") (match_code "subreg,reg")
{ {
...@@ -332,8 +317,7 @@ ...@@ -332,8 +317,7 @@
return 0; return 0;
}) })
;; TODO: Add a comment here. ;; Returns true if OP is the FPSCR.
(define_predicate "fpscr_operand" (define_predicate "fpscr_operand"
(match_code "reg") (match_code "reg")
{ {
...@@ -382,8 +366,7 @@ ...@@ -382,8 +366,7 @@
(and (match_code "const_double") (and (match_code "const_double")
(match_test "op == sh_fsca_int2sf ()"))) (match_test "op == sh_fsca_int2sf ()")))
;; TODO: Add a comment here. ;; Returns true if OP is an operand that is zero extended during an operation.
(define_predicate "general_extend_operand" (define_predicate "general_extend_operand"
(match_code "subreg,reg,mem,truncate") (match_code "subreg,reg,mem,truncate")
{ {
...@@ -423,9 +406,9 @@ ...@@ -423,9 +406,9 @@
;; Returns 1 if OP can be source of a simple move operation. Same as ;; Returns 1 if OP can be source of a simple move operation. Same as
;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
;; are subregs of system registers. ;; are subregs of system registers.
(define_predicate "general_movsrc_operand" (define_predicate "general_movsrc_operand"
(match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector") (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,
const,const_vector")
{ {
if (t_reg_operand (op, mode)) if (t_reg_operand (op, mode))
return 0; return 0;
...@@ -482,7 +465,6 @@ ...@@ -482,7 +465,6 @@
}) })
;; Returns 1 if OP is a MEM that does not use displacement addressing. ;; Returns 1 if OP is a MEM that does not use displacement addressing.
(define_predicate "movsrc_no_disp_mem_operand" (define_predicate "movsrc_no_disp_mem_operand"
(match_code "mem") (match_code "mem")
{ {
...@@ -491,7 +473,6 @@ ...@@ -491,7 +473,6 @@
;; Returns 1 if OP can be a destination of a move. Same as ;; Returns 1 if OP can be a destination of a move. Same as
;; general_operand, but no preinc allowed. ;; general_operand, but no preinc allowed.
(define_predicate "general_movdst_operand" (define_predicate "general_movdst_operand"
(match_code "subreg,reg,mem") (match_code "subreg,reg,mem")
{ {
...@@ -534,7 +515,6 @@ ...@@ -534,7 +515,6 @@
}) })
;; Returns 1 if OP is a POST_INC on stack pointer register. ;; Returns 1 if OP is a POST_INC on stack pointer register.
(define_predicate "sh_no_delay_pop_operand" (define_predicate "sh_no_delay_pop_operand"
(match_code "mem") (match_code "mem")
{ {
...@@ -551,7 +531,6 @@ ...@@ -551,7 +531,6 @@
}) })
;; Returns 1 if OP is a MEM that can be source of a simple move operation. ;; Returns 1 if OP is a MEM that can be source of a simple move operation.
(define_predicate "unaligned_load_operand" (define_predicate "unaligned_load_operand"
(match_code "mem") (match_code "mem")
{ {
...@@ -599,13 +578,12 @@ ...@@ -599,13 +578,12 @@
&& sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true); && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true);
}) })
;; TODO: Add a comment here. ;; Returns true if OP is some kind of greater comparision.
(define_predicate "greater_comparison_operator" (define_predicate "greater_comparison_operator"
(match_code "gt,ge,gtu,geu")) (match_code "gt,ge,gtu,geu"))
;; TODO: Add a comment here. ;; Returns true if OP is an operand suitable for shmedia reload_inqi and
;; reload_inhi insns.
(define_predicate "inqhi_operand" (define_predicate "inqhi_operand"
(match_code "truncate") (match_code "truncate")
{ {
...@@ -617,28 +595,26 @@ ...@@ -617,28 +595,26 @@
return REG_P (op) && FP_REGISTER_P (REGNO (op)); return REG_P (op) && FP_REGISTER_P (REGNO (op));
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a general purpose integer register.
;; This predicate is currently unused.
(define_special_predicate "int_gpr_dest" ;;(define_special_predicate "int_gpr_dest"
(match_code "subreg,reg") ;; (match_code "subreg,reg")
{ ;;{
enum machine_mode op_mode = GET_MODE (op); ;; enum machine_mode op_mode = GET_MODE (op);
;;
if (GET_MODE_CLASS (op_mode) != MODE_INT ;; if (GET_MODE_CLASS (op_mode) != MODE_INT
|| GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD) ;; || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
return 0; ;; return 0;
if (! reload_completed) ;; if (! reload_completed)
return 0; ;; return 0;
return true_regnum (op) <= LAST_GENERAL_REG; ;; return true_regnum (op) <= LAST_GENERAL_REG;
}) ;;})
;; TODO: Add a comment here. ;; Returns true if OP is some kind of less comparison.
(define_predicate "less_comparison_operator" (define_predicate "less_comparison_operator"
(match_code "lt,le,ltu,leu")) (match_code "lt,le,ltu,leu"))
;; Returns 1 if OP is a valid source operand for a logical operation. ;; Returns 1 if OP is a valid source operand for a logical operation.
(define_predicate "logical_operand" (define_predicate "logical_operand"
(match_code "subreg,reg,const_int") (match_code "subreg,reg,const_int")
{ {
...@@ -678,14 +654,12 @@ ...@@ -678,14 +654,12 @@
return 0; return 0;
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a logical operator.
(define_predicate "logical_operator" (define_predicate "logical_operator"
(match_code "and,ior,xor")) (match_code "and,ior,xor"))
;; Like arith_reg_operand, but for register source operands of narrow ;; Like arith_reg_operand, but for register source operands of narrow
;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs. ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
(define_predicate "logical_reg_operand" (define_predicate "logical_reg_operand"
(match_code "subreg,reg") (match_code "subreg,reg")
{ {
...@@ -697,8 +671,7 @@ ...@@ -697,8 +671,7 @@
return arith_reg_operand (op, mode); return arith_reg_operand (op, mode);
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a valid bit offset value for the shmedia mextr insns.
(define_predicate "mextr_bit_offset" (define_predicate "mextr_bit_offset"
(match_code "const_int") (match_code "const_int")
{ {
...@@ -710,19 +683,19 @@ ...@@ -710,19 +683,19 @@
return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0; return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a constant -1, 0 or an zero extended register that
;; can be used as an operator in the *subsi3_media insn.
(define_predicate "minuend_operand" (define_predicate "minuend_operand"
(match_code "subreg,reg,truncate,const_int") (match_code "subreg,reg,truncate,const_int")
{ {
return op == constm1_rtx || extend_reg_or_0_operand (op, mode); return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a noncommutative floating point operator.
;; This predicate is currently unused.
(define_predicate "noncommutative_float_operator" ;;(define_predicate "noncommutative_float_operator"
(and (match_code "minus,div") ;; (and (match_code "minus,div")
(match_test "GET_MODE (op) == mode"))) ;; (match_test "GET_MODE (op) == mode")))
;; UNORDERED is only supported on SHMEDIA. ;; UNORDERED is only supported on SHMEDIA.
...@@ -735,8 +708,7 @@ ...@@ -735,8 +708,7 @@
(ior (match_operand 0 "equality_comparison_operator") (ior (match_operand 0 "equality_comparison_operator")
(match_operand 0 "greater_comparison_operator"))) (match_operand 0 "greater_comparison_operator")))
;; TODO: Add a comment here. ;; Returns true if OP is a constant vector.
(define_predicate "sh_const_vec" (define_predicate "sh_const_vec"
(match_code "const_vector") (match_code "const_vector")
{ {
...@@ -755,7 +727,6 @@ ...@@ -755,7 +727,6 @@
;; Determine if OP is a constant vector matching MODE with only one ;; Determine if OP is a constant vector matching MODE with only one
;; element that is not a sign extension. Two byte-sized elements ;; element that is not a sign extension. Two byte-sized elements
;; count as one. ;; count as one.
(define_predicate "sh_1el_vec" (define_predicate "sh_1el_vec"
(match_code "const_vector") (match_code "const_vector")
{ {
...@@ -789,7 +760,6 @@ ...@@ -789,7 +760,6 @@
;; Like register_operand, but take into account that SHMEDIA can use ;; Like register_operand, but take into account that SHMEDIA can use
;; the constant zero like a general register. ;; the constant zero like a general register.
(define_predicate "sh_register_operand" (define_predicate "sh_register_operand"
(match_code "reg,subreg,const_int,const_double") (match_code "reg,subreg,const_int,const_double")
{ {
...@@ -798,8 +768,8 @@ ...@@ -798,8 +768,8 @@
return register_operand (op, mode); return register_operand (op, mode);
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a vector which is composed of one element that is
;; repeated.
(define_predicate "sh_rep_vec" (define_predicate "sh_rep_vec"
(match_code "const_vector,parallel") (match_code "const_vector,parallel")
{ {
...@@ -826,10 +796,10 @@ ...@@ -826,10 +796,10 @@
return 1; return 1;
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a valid shift count operand for shift operations.
(define_predicate "shift_count_operand" (define_predicate "shift_count_operand"
(match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend") (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,
zero_extend,sign_extend")
{ {
/* Allow T_REG as shift count for dynamic shifts, although it is not /* Allow T_REG as shift count for dynamic shifts, although it is not
really possible. It will then be copied to a general purpose reg. */ really possible. It will then be copied to a general purpose reg. */
...@@ -844,8 +814,8 @@ ...@@ -844,8 +814,8 @@
: shift_count_reg_operand (op, mode)); : shift_count_reg_operand (op, mode));
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a valid shift count operand in a register which can
;; be used by shmedia shift insns.
(define_predicate "shift_count_reg_operand" (define_predicate "shift_count_reg_operand"
(match_code "subreg,reg,zero_extend,sign_extend") (match_code "subreg,reg,zero_extend,sign_extend")
{ {
...@@ -890,19 +860,16 @@ ...@@ -890,19 +860,16 @@
(ior (match_test "! satisfies_constraint_P27 (op)") (ior (match_test "! satisfies_constraint_P27 (op)")
(match_test "satisfies_constraint_M (op)")))) (match_test "satisfies_constraint_M (op)"))))
;; TODO: Add a comment here. ;; Returns true if OP is some kind of a shift operator.
(define_predicate "shift_operator" (define_predicate "shift_operator"
(match_code "ashift,ashiftrt,lshiftrt")) (match_code "ashift,ashiftrt,lshiftrt"))
;; TODO: Add a comment here. ;; Returns true if OP is a symbol reference.
(define_predicate "symbol_ref_operand" (define_predicate "symbol_ref_operand"
(match_code "symbol_ref")) (match_code "symbol_ref"))
;; Same as target_reg_operand, except that label_refs and symbol_refs ;; Same as target_reg_operand, except that label_refs and symbol_refs
;; are accepted before reload. ;; are accepted before reload.
(define_special_predicate "target_operand" (define_special_predicate "target_operand"
(match_code "subreg,reg,label_ref,symbol_ref,const,unspec") (match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
{ {
...@@ -916,8 +883,7 @@ ...@@ -916,8 +883,7 @@
return target_reg_operand (op, mode); return target_reg_operand (op, mode);
}) })
;; Accept pseudos and branch target registers. ;; A predicate that accepts pseudos and branch target registers.
(define_special_predicate "target_reg_operand" (define_special_predicate "target_reg_operand"
(match_code "subreg,reg") (match_code "subreg,reg")
{ {
...@@ -942,8 +908,7 @@ ...@@ -942,8 +908,7 @@
return 0; return 0;
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a valid operand for the shmedia mperm.w insn.
(define_special_predicate "trunc_hi_operand" (define_special_predicate "trunc_hi_operand"
(match_code "subreg,reg,truncate") (match_code "subreg,reg,truncate")
{ {
...@@ -955,8 +920,8 @@ ...@@ -955,8 +920,8 @@
return extend_reg_operand (op, mode); return extend_reg_operand (op, mode);
}) })
;; Return 1 of OP is an address suitable for an unaligned access instruction. ;; Returns true if OP is an address suitable for an unaligned access
;; instruction.
(define_special_predicate "ua_address_operand" (define_special_predicate "ua_address_operand"
(match_code "subreg,reg,plus") (match_code "subreg,reg,plus")
{ {
...@@ -966,22 +931,19 @@ ...@@ -966,22 +931,19 @@
return address_operand (op, QImode); return address_operand (op, QImode);
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a valid offset for an unaligned memory address.
(define_predicate "ua_offset" (define_predicate "ua_offset"
(match_code "const_int") (match_code "const_int")
{ {
return satisfies_constraint_I06 (op); return satisfies_constraint_I06 (op);
}) })
;; TODO: Add a comment here. ;; Returns true if OP is a floating point operator with one operand.
(define_predicate "unary_float_operator" (define_predicate "unary_float_operator"
(and (match_code "abs,neg,sqrt") (and (match_code "abs,neg,sqrt")
(match_test "GET_MODE (op) == mode"))) (match_test "GET_MODE (op) == mode")))
;; Return 1 if OP is a valid source operand for xor. ;; Return 1 if OP is a valid source operand for xor.
(define_predicate "xor_operand" (define_predicate "xor_operand"
(match_code "subreg,reg,const_int") (match_code "subreg,reg,const_int")
{ {
...@@ -1080,7 +1042,7 @@ ...@@ -1080,7 +1042,7 @@
return sh_eval_treg_value (op) >= 0; return sh_eval_treg_value (op) >= 0;
}) })
;; Returns true of OP is arith_reg_operand or t_reg_operand. ;; Returns true if OP is arith_reg_operand or t_reg_operand.
(define_predicate "arith_reg_or_t_reg_operand" (define_predicate "arith_reg_or_t_reg_operand"
(ior (match_operand 0 "arith_reg_operand") (ior (match_operand 0 "arith_reg_operand")
(match_operand 0 "t_reg_operand"))) (match_operand 0 "t_reg_operand")))
...@@ -1124,7 +1086,7 @@ ...@@ -1124,7 +1086,7 @@
}) })
;; A predicate that determines whether a given constant is a valid ;; A predicate that determines whether a given constant is a valid
;; displacement for a gbr load/store of the specified mode. ;; displacement for a GBR load/store of the specified mode.
(define_predicate "gbr_displacement" (define_predicate "gbr_displacement"
(match_code "const_int") (match_code "const_int")
{ {
......
gcc/config/sh/sh-protos.h
...@@ -212,7 +212,8 @@ extern void sh_pr_nosave_low_regs (struct cpp_reader *); ...@@ -212,7 +212,8 @@ extern void sh_pr_nosave_low_regs (struct cpp_reader *);
extern rtx function_symbol (rtx, const char *, enum sh_function_kind); extern rtx function_symbol (rtx, const char *, enum sh_function_kind);
extern rtx sh_get_pr_initial_val (void); extern rtx sh_get_pr_initial_val (void);
extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, signed int, enum machine_mode); extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree,
signed int, enum machine_mode);
extern rtx sh_dwarf_register_span (rtx); extern rtx sh_dwarf_register_span (rtx);
extern rtx replace_n_hard_rtx (rtx, rtx *, int , int); extern rtx replace_n_hard_rtx (rtx, rtx *, int , int);
......
gcc/config/sh/sh.c
...@@ -112,7 +112,7 @@ static int r0_life_regions; ...@@ -112,7 +112,7 @@ static int r0_life_regions;
/* If true, skip cycles for Q -> R movement. */ /* If true, skip cycles for Q -> R movement. */
static int skip_cycles = 0; static int skip_cycles = 0;
/* Cached value of can_issue_more. This is cached in sh_variable_issue hook /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
and returned from sh_reorder2. */ and returned from sh_reorder2. */
static short cached_can_issue_more; static short cached_can_issue_more;
...@@ -121,7 +121,6 @@ static unsigned int unspec_bbr_uid = 1; ...@@ -121,7 +121,6 @@ static unsigned int unspec_bbr_uid = 1;
/* Provides the class number of the smallest class containing /* Provides the class number of the smallest class containing
reg number. */ reg number. */
enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] = enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
{ {
R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
...@@ -198,7 +197,8 @@ static int calc_live_regs (HARD_REG_SET *); ...@@ -198,7 +197,8 @@ static int calc_live_regs (HARD_REG_SET *);
static HOST_WIDE_INT rounded_frame_size (int); static HOST_WIDE_INT rounded_frame_size (int);
static bool sh_frame_pointer_required (void); static bool sh_frame_pointer_required (void);
static rtx mark_constant_pool_use (rtx); static rtx mark_constant_pool_use (rtx);
static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *); static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree,
int, bool *);
static tree sh_handle_resbank_handler_attribute (tree *, tree, static tree sh_handle_resbank_handler_attribute (tree *, tree,
tree, int, bool *); tree, int, bool *);
static tree sh2a_handle_function_vector_handler_attribute (tree *, tree, static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
...@@ -242,7 +242,8 @@ static bool sh_ms_bitfield_layout_p (const_tree); ...@@ -242,7 +242,8 @@ static bool sh_ms_bitfield_layout_p (const_tree);
static void sh_init_builtins (void); static void sh_init_builtins (void);
static tree sh_builtin_decl (unsigned, bool); static tree sh_builtin_decl (unsigned, bool);
static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int); static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree);
static void sh_file_start (void); static void sh_file_start (void);
static bool flow_dependent_p (rtx, rtx); static bool flow_dependent_p (rtx, rtx);
static void flow_dependent_p_1 (rtx, const_rtx, void *); static void flow_dependent_p_1 (rtx, const_rtx, void *);
...@@ -277,7 +278,8 @@ static bool sh_function_value_regno_p (const unsigned int); ...@@ -277,7 +278,8 @@ static bool sh_function_value_regno_p (const unsigned int);
static rtx sh_libcall_value (enum machine_mode, const_rtx); static rtx sh_libcall_value (enum machine_mode, const_rtx);
static bool sh_return_in_memory (const_tree, const_tree); static bool sh_return_in_memory (const_tree, const_tree);
static rtx sh_builtin_saveregs (void); static rtx sh_builtin_saveregs (void);
static void sh_setup_incoming_varargs (cumulative_args_t, enum machine_mode, tree, int *, int); static void sh_setup_incoming_varargs (cumulative_args_t, enum machine_mode,
tree, int *, int);
static bool sh_strict_argument_naming (cumulative_args_t); static bool sh_strict_argument_naming (cumulative_args_t);
static bool sh_pretend_outgoing_varargs_named (cumulative_args_t); static bool sh_pretend_outgoing_varargs_named (cumulative_args_t);
static tree sh_build_builtin_va_list (void); static tree sh_build_builtin_va_list (void);
...@@ -376,7 +378,8 @@ static const struct attribute_spec sh_attribute_table[] = ...@@ -376,7 +378,8 @@ static const struct attribute_spec sh_attribute_table[] =
#define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
hook_bool_const_tree_hwi_hwi_const_tree_true
#undef TARGET_ASM_FILE_START #undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START sh_file_start #define TARGET_ASM_FILE_START sh_file_start
...@@ -463,7 +466,7 @@ static const struct attribute_spec sh_attribute_table[] = ...@@ -463,7 +466,7 @@ static const struct attribute_spec sh_attribute_table[] =
#define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
#undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \ #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
sh_optimize_target_register_callee_saved sh_optimize_target_register_callee_saved
#undef TARGET_MS_BITFIELD_LAYOUT_P #undef TARGET_MS_BITFIELD_LAYOUT_P
#define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
...@@ -591,7 +594,7 @@ static const struct attribute_spec sh_attribute_table[] = ...@@ -591,7 +594,7 @@ static const struct attribute_spec sh_attribute_table[] =
#define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison #define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison
/* Machine-specific symbol_ref flags. */ /* Machine-specific symbol_ref flags. */
#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0) #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
/* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
is used by optabs.c atomic op expansion code as well as in sync.md. */ is used by optabs.c atomic op expansion code as well as in sync.md. */
...@@ -681,7 +684,7 @@ got_mode_name:; ...@@ -681,7 +684,7 @@ got_mode_name:;
} }
else else
err_ret ("unknown parameter \"%s\" in atomic model option", err_ret ("unknown parameter \"%s\" in atomic model option",
tokens[i].c_str ()); tokens[i].c_str ());
} }
/* Check that the selection makes sense. */ /* Check that the selection makes sense. */
...@@ -835,7 +838,7 @@ sh_option_override (void) ...@@ -835,7 +838,7 @@ sh_option_override (void)
/* ??? Should we use the integer SHmedia function instead? */ /* ??? Should we use the integer SHmedia function instead? */
else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
sh_div_strategy = SH_DIV_CALL_FP; sh_div_strategy = SH_DIV_CALL_FP;
/* SH1 .. SH3 cores often go into small-footprint systems, so /* SH1 .. SH3 cores often go into small-footprint systems, so
default to the smallest implementation available. */ default to the smallest implementation available. */
else if (TARGET_SH2) /* ??? EXPERIMENTAL */ else if (TARGET_SH2) /* ??? EXPERIMENTAL */
sh_div_strategy = SH_DIV_CALL_TABLE; sh_div_strategy = SH_DIV_CALL_TABLE;
...@@ -881,7 +884,7 @@ sh_option_override (void) ...@@ -881,7 +884,7 @@ sh_option_override (void)
|| (TARGET_SHMEDIA && !TARGET_PT_FIXED)) || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
flag_no_function_cse = 1; flag_no_function_cse = 1;
if (targetm.small_register_classes_for_mode_p (VOIDmode)) \ if (targetm.small_register_classes_for_mode_p (VOIDmode))
{ {
/* Never run scheduling before reload, since that can /* Never run scheduling before reload, since that can
break global alloc, and generates slower code anyway due break global alloc, and generates slower code anyway due
...@@ -891,16 +894,17 @@ sh_option_override (void) ...@@ -891,16 +894,17 @@ sh_option_override (void)
the target hooks if pressure is high. We can not do this for the target hooks if pressure is high. We can not do this for
PIC, SH3 and lower as they give spill failures for R0. */ PIC, SH3 and lower as they give spill failures for R0. */
if (!TARGET_HARD_SH4 || flag_pic) if (!TARGET_HARD_SH4 || flag_pic)
flag_schedule_insns = 0; flag_schedule_insns = 0;
/* ??? Current exception handling places basic block boundaries /* ??? Current exception handling places basic block boundaries
after call_insns. It causes the high pressure on R0 and gives after call_insns. It causes the high pressure on R0 and gives
spill failures for R0 in reload. See PR 22553 and the thread spill failures for R0 in reload. See PR 22553 and the thread
on gcc-patches on gcc-patches
<http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
else if (flag_exceptions) else if (flag_exceptions)
{ {
if (flag_schedule_insns && global_options_set.x_flag_schedule_insns) if (flag_schedule_insns && global_options_set.x_flag_schedule_insns)
warning (0, "ignoring -fschedule-insns because of exception handling bug"); warning (0, "ignoring -fschedule-insns because of exception "
"handling bug");
flag_schedule_insns = 0; flag_schedule_insns = 0;
} }
else if (flag_schedule_insns else if (flag_schedule_insns
...@@ -985,10 +989,9 @@ sh_option_override (void) ...@@ -985,10 +989,9 @@ sh_option_override (void)
compilation unit. */ compilation unit. */
if (TARGET_RELAX) if (TARGET_RELAX)
{ {
int min_align int min_align = align_loops > align_jumps ? align_loops : align_jumps;
= align_loops > align_jumps ? align_loops : align_jumps;
/* Also take possible .long constants / mova tables int account. */ /* Also take possible .long constants / mova tables into account. */
if (min_align < 4) if (min_align < 4)
min_align = 4; min_align = 4;
if (align_functions < min_align) if (align_functions < min_align)
...@@ -1031,7 +1034,6 @@ sh_option_override (void) ...@@ -1031,7 +1034,6 @@ sh_option_override (void)
} }
/* Print the operand address in x to the stream. */ /* Print the operand address in x to the stream. */
static void static void
sh_print_operand_address (FILE *stream, rtx x) sh_print_operand_address (FILE *stream, rtx x)
{ {
...@@ -1110,7 +1112,6 @@ sh_print_operand_address (FILE *stream, rtx x) ...@@ -1110,7 +1112,6 @@ sh_print_operand_address (FILE *stream, rtx x)
't' print a memory address which is a register. 't' print a memory address which is a register.
'u' prints the lowest 16 bits of CONST_INT, as an unsigned value. 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
'o' output an operator. */ 'o' output an operator. */
static void static void
sh_print_operand (FILE *stream, rtx x, int code) sh_print_operand (FILE *stream, rtx x, int code)
{ {
...@@ -1134,7 +1135,7 @@ sh_print_operand (FILE *stream, rtx x, int code) ...@@ -1134,7 +1135,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
trapa_attr = lookup_attribute ("trap_exit", trapa_attr = lookup_attribute ("trap_exit",
DECL_ATTRIBUTES (current_function_decl)); DECL_ATTRIBUTES (current_function_decl));
if (trapa_attr) if (trapa_attr)
fprintf (stream, "trapa #%ld", fprintf (stream, "trapa #%ld",
(long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr)))); (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
else if (sh_cfun_interrupt_handler_p ()) else if (sh_cfun_interrupt_handler_p ())
{ {
...@@ -1469,11 +1470,10 @@ static bool ...@@ -1469,11 +1470,10 @@ static bool
sh_print_operand_punct_valid_p (unsigned char code) sh_print_operand_punct_valid_p (unsigned char code)
{ {
return (code == '.' || code == '#' || code == '@' || code == ',' return (code == '.' || code == '#' || code == '@' || code == ','
|| code == '$' || code == '\'' || code == '>'); || code == '$' || code == '\'' || code == '>');
} }
/* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
static bool static bool
sh_asm_output_addr_const_extra (FILE *file, rtx x) sh_asm_output_addr_const_extra (FILE *file, rtx x)
{ {
...@@ -1535,9 +1535,9 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x) ...@@ -1535,9 +1535,9 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x)
shift = XVECEXP (x, 0, 1); shift = XVECEXP (x, 0, 1);
fputc ('(', file); fputc ('(', file);
if (shift != const0_rtx) if (shift != const0_rtx)
fputc ('(', file); fputc ('(', file);
if (GET_CODE (val) == CONST if (GET_CODE (val) == CONST
|| GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ)
{ {
fputc ('(', file); fputc ('(', file);
output_addr_const (file, val); output_addr_const (file, val);
...@@ -1581,7 +1581,6 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x) ...@@ -1581,7 +1581,6 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x)
return false; return false;
} }
/* Encode symbol attributes of a SYMBOL_REF into its /* Encode symbol attributes of a SYMBOL_REF into its
SYMBOL_REF_FLAGS. */ SYMBOL_REF_FLAGS. */
static void static void
...@@ -1609,7 +1608,6 @@ force_into (rtx value, rtx target) ...@@ -1609,7 +1608,6 @@ force_into (rtx value, rtx target)
OPERANDS[1] is the source. OPERANDS[1] is the source.
OPERANDS[2] is the size. OPERANDS[2] is the size.
OPERANDS[3] is the alignment safe to use. */ OPERANDS[3] is the alignment safe to use. */
bool bool
expand_block_move (rtx *operands) expand_block_move (rtx *operands)
{ {
...@@ -1748,7 +1746,6 @@ expand_block_move (rtx *operands) ...@@ -1748,7 +1746,6 @@ expand_block_move (rtx *operands)
/* Prepare operands for a move define_expand; specifically, one of the /* Prepare operands for a move define_expand; specifically, one of the
operands must be in a register. */ operands must be in a register. */
void void
prepare_move_operands (rtx operands[], enum machine_mode mode) prepare_move_operands (rtx operands[], enum machine_mode mode)
{ {
...@@ -1947,9 +1944,9 @@ sh_canonicalize_comparison (enum rtx_code& cmp, rtx& op0, rtx& op1, ...@@ -1947,9 +1944,9 @@ sh_canonicalize_comparison (enum rtx_code& cmp, rtx& op0, rtx& op1,
if (CONST_INT_P (op1)) if (CONST_INT_P (op1))
{ {
/* Try to adjust the constant operand in such a way that available /* Try to adjust the constant operand in such a way that available
comparison insns can be utilized better and the constant can be comparison insns can be utilized better and the constant can be
loaded with a 'mov #imm,Rm' insn. This avoids a load from the loaded with a 'mov #imm,Rm' insn. This avoids a load from the
constant pool. */ constant pool. */
const HOST_WIDE_INT val = INTVAL (op1); const HOST_WIDE_INT val = INTVAL (op1);
/* x > -1 --> x >= 0 /* x > -1 --> x >= 0
...@@ -2027,6 +2024,7 @@ sh_canonicalize_comparison (int *code, rtx *op0, rtx *op1, ...@@ -2027,6 +2024,7 @@ sh_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
VOIDmode, op0_preserve_value); VOIDmode, op0_preserve_value);
*code = (int)tmp_code; *code = (int)tmp_code;
} }
enum rtx_code enum rtx_code
prepare_cbranch_operands (rtx *operands, enum machine_mode mode, prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
enum rtx_code comparison) enum rtx_code comparison)
...@@ -2089,8 +2087,8 @@ expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability) ...@@ -2089,8 +2087,8 @@ expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
default: ; default: ;
} }
emit_insn (gen_rtx_SET (VOIDmode, get_t_reg_rtx (), emit_insn (gen_rtx_SET (VOIDmode, get_t_reg_rtx (),
gen_rtx_fmt_ee (comparison, SImode, gen_rtx_fmt_ee (comparison, SImode,
operands[1], operands[2]))); operands[1], operands[2])));
rtx jump = emit_jump_insn (branch_expander (operands[3])); rtx jump = emit_jump_insn (branch_expander (operands[3]));
if (probability >= 0) if (probability >= 0)
add_reg_note (jump, REG_BR_PROB, GEN_INT (probability)); add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
...@@ -2113,7 +2111,6 @@ expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability) ...@@ -2113,7 +2111,6 @@ expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
the same. Thus, we can't really tell anything here; the same. Thus, we can't really tell anything here;
assuming random distribution is at least simple. assuming random distribution is at least simple.
*/ */
bool bool
expand_cbranchdi4 (rtx *operands, enum rtx_code comparison) expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
{ {
...@@ -2346,7 +2343,7 @@ sh_emit_set_t_insn (rtx insn, enum machine_mode mode) ...@@ -2346,7 +2343,7 @@ sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT) if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
{ {
insn = gen_rtx_PARALLEL (VOIDmode, insn = gen_rtx_PARALLEL (VOIDmode,
gen_rtvec (2, insn, gen_rtvec (2, insn,
gen_rtx_USE (VOIDmode, get_fpscr_rtx ()))); gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
(mode == SFmode ? emit_sf_insn : emit_df_insn) (insn); (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
} }
...@@ -2463,7 +2460,6 @@ sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code, ...@@ -2463,7 +2460,6 @@ sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
} }
/* Called from the md file, set up the operands of a compare instruction. */ /* Called from the md file, set up the operands of a compare instruction. */
void void
sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode) sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
{ {
...@@ -2482,10 +2478,10 @@ sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode) ...@@ -2482,10 +2478,10 @@ sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
else else
{ {
if (code != EQ || mode == DImode) if (code != EQ || mode == DImode)
{ {
/* Force args into regs, since we can't use constants here. */ /* Force args into regs, since we can't use constants here. */
op0 = force_reg (mode, op0); op0 = force_reg (mode, op0);
if (op1 != const0_rtx || code == GTU || code == GEU) if (op1 != const0_rtx || code == GTU || code == GEU)
op1 = force_reg (mode, op1); op1 = force_reg (mode, op1);
} }
} }
...@@ -2504,7 +2500,7 @@ sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode) ...@@ -2504,7 +2500,7 @@ sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
if (code == GE) if (code == GE)
{ {
gcc_assert (TARGET_IEEE && TARGET_SH2E); gcc_assert (TARGET_IEEE && TARGET_SH2E);
need_ccmpeq = true; need_ccmpeq = true;
code = GT; code = GT;
} }
...@@ -2573,20 +2569,20 @@ sh_emit_compare_and_set (rtx *operands, enum machine_mode mode) ...@@ -2573,20 +2569,20 @@ sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
tem = op0, op0 = op1, op1 = tem; tem = op0, op0 = op1, op1 = tem;
} }
if (code == GE) if (code == GE)
{ {
if (TARGET_IEEE) if (TARGET_IEEE)
{ {
lab = gen_label_rtx (); lab = gen_label_rtx ();
sh_emit_scc_to_t (EQ, op0, op1); sh_emit_scc_to_t (EQ, op0, op1);
emit_jump_insn (gen_branch_true (lab)); emit_jump_insn (gen_branch_true (lab));
code = GT; code = GT;
} }
else else
{ {
code = LT; code = LT;
invert = true; invert = true;
} }
} }
} }
if (code == NE) if (code == NE)
...@@ -2610,7 +2606,6 @@ sh_emit_compare_and_set (rtx *operands, enum machine_mode mode) ...@@ -2610,7 +2606,6 @@ sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
Since the SH cannot move a DI or DF in one instruction, we have Since the SH cannot move a DI or DF in one instruction, we have
to take care when we see overlapping source and dest registers. */ to take care when we see overlapping source and dest registers. */
const char * const char *
output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
enum machine_mode mode) enum machine_mode mode)
...@@ -2632,7 +2627,6 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], ...@@ -2632,7 +2627,6 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
/* When mov.d r1,r2 do r2->r3 then r1->r2; /* When mov.d r1,r2 do r2->r3 then r1->r2;
when mov.d r1,r0 do r1->r0 then r2->r1. */ when mov.d r1,r0 do r1->r0 then r2->r1. */
if (REGNO (src) + 1 == REGNO (dst)) if (REGNO (src) + 1 == REGNO (dst))
return "mov %T1,%T0" "\n" return "mov %T1,%T0" "\n"
" mov %1,%0"; " mov %1,%0";
...@@ -2700,7 +2694,6 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], ...@@ -2700,7 +2694,6 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
/* Print an instruction which would have gone into a delay slot after /* Print an instruction which would have gone into a delay slot after
another instruction, but couldn't because the other instruction expanded another instruction, but couldn't because the other instruction expanded
into a sequence where putting the slot insn at the end wouldn't work. */ into a sequence where putting the slot insn at the end wouldn't work. */
static void static void
print_slot (rtx insn) print_slot (rtx insn)
{ {
...@@ -2811,11 +2804,9 @@ output_far_jump (rtx insn, rtx op) ...@@ -2811,11 +2804,9 @@ output_far_jump (rtx insn, rtx op)
/* Local label counter, used for constants in the pool and inside /* Local label counter, used for constants in the pool and inside
pattern branches. */ pattern branches. */
static int lf = 100; static int lf = 100;
/* Output code for ordinary branches. */ /* Output code for ordinary branches. */
const char * const char *
output_branch (int logic, rtx insn, rtx *operands) output_branch (int logic, rtx insn, rtx *operands)
{ {
...@@ -2829,7 +2820,6 @@ output_branch (int logic, rtx insn, rtx *operands) ...@@ -2829,7 +2820,6 @@ output_branch (int logic, rtx insn, rtx *operands)
It can also happen when other condbranches hoist delay slot insn It can also happen when other condbranches hoist delay slot insn
from their destination, thus leading to code size increase. from their destination, thus leading to code size increase.
But the branch will still be in the range -4092..+4098 bytes. */ But the branch will still be in the range -4092..+4098 bytes. */
if (! TARGET_RELAX) if (! TARGET_RELAX)
{ {
int label = lf++; int label = lf++;
...@@ -2958,7 +2948,6 @@ output_ieee_ccmpeq (rtx insn, rtx *operands) ...@@ -2958,7 +2948,6 @@ output_ieee_ccmpeq (rtx insn, rtx *operands)
} }
/* Output the start of the assembler file. */ /* Output the start of the assembler file. */
static void static void
sh_file_start (void) sh_file_start (void)
{ {
...@@ -2992,7 +2981,6 @@ sh_file_start (void) ...@@ -2992,7 +2981,6 @@ sh_file_start (void)
} }
/* Check if PAT includes UNSPEC_CALLER unspec pattern. */ /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
static bool static bool
unspec_caller_rtx_p (rtx pat) unspec_caller_rtx_p (rtx pat)
{ {
...@@ -3013,7 +3001,6 @@ unspec_caller_rtx_p (rtx pat) ...@@ -3013,7 +3001,6 @@ unspec_caller_rtx_p (rtx pat)
/* Indicate that INSN cannot be duplicated. This is true for insn /* Indicate that INSN cannot be duplicated. This is true for insn
that generates a unique label. */ that generates a unique label. */
static bool static bool
sh_cannot_copy_insn_p (rtx insn) sh_cannot_copy_insn_p (rtx insn)
{ {
...@@ -3156,6 +3143,8 @@ sh_ashlsi_clobbers_t_reg_p (rtx shift_amount) ...@@ -3156,6 +3143,8 @@ sh_ashlsi_clobbers_t_reg_p (rtx shift_amount)
& ASHL_CLOBBERS_T) != 0; & ASHL_CLOBBERS_T) != 0;
} }
/* Return true if a logical right shift consisting of 1/2/8/16 shift
instructions will clobber the T bit. */
bool bool
sh_lshrsi_clobbers_t_reg_p (rtx shift_amount) sh_lshrsi_clobbers_t_reg_p (rtx shift_amount)
{ {
...@@ -3194,12 +3183,12 @@ sh_dynamicalize_shift_p (rtx count) ...@@ -3194,12 +3183,12 @@ sh_dynamicalize_shift_p (rtx count)
} }
/* Assuming we have a value that has been sign-extended by at least one bit, /* Assuming we have a value that has been sign-extended by at least one bit,
can we use the ext_shift_amounts with the last shift turned to an arithmetic shift can we use the ext_shift_amounts with the last shift turned to an
to shift it by N without data loss, and quicker than by other means? */ arithmetic shift to shift it by N without data loss, and quicker than by
other means? */
#define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15) #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
/* Return the cost of a shift. */ /* Return the cost of a shift. */
static inline int static inline int
shiftcosts (rtx x) shiftcosts (rtx x)
{ {
...@@ -3240,7 +3229,6 @@ shiftcosts (rtx x) ...@@ -3240,7 +3229,6 @@ shiftcosts (rtx x)
} }
/* Return the cost of an AND/XOR/IOR operation. */ /* Return the cost of an AND/XOR/IOR operation. */
static inline int static inline int
and_xor_ior_costs (rtx x, int code) and_xor_ior_costs (rtx x, int code)
{ {
...@@ -3284,7 +3272,6 @@ and_xor_ior_costs (rtx x, int code) ...@@ -3284,7 +3272,6 @@ and_xor_ior_costs (rtx x, int code)
} }
/* Return the cost of an addition or a subtraction. */ /* Return the cost of an addition or a subtraction. */
static inline int static inline int
addsubcosts (rtx x) addsubcosts (rtx x)
{ {
...@@ -3314,7 +3301,7 @@ addsubcosts (rtx x) ...@@ -3314,7 +3301,7 @@ addsubcosts (rtx x)
case CONST_INT: case CONST_INT:
if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)))) if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
return 2; return 2;
else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16)) else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
return 3; return 3;
else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16)) else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
...@@ -3368,7 +3355,6 @@ multcosts (rtx x ATTRIBUTE_UNUSED) ...@@ -3368,7 +3355,6 @@ multcosts (rtx x ATTRIBUTE_UNUSED)
/* Compute a (partial) cost for rtx X. Return true if the complete /* Compute a (partial) cost for rtx X. Return true if the complete
cost has been computed, and false if subexpressions should be cost has been computed, and false if subexpressions should be
scanned. In either case, *TOTAL contains the cost result. */ scanned. In either case, *TOTAL contains the cost result. */
static bool static bool
sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
int *total, bool speed ATTRIBUTE_UNUSED) int *total, bool speed ATTRIBUTE_UNUSED)
...@@ -3470,7 +3456,7 @@ sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, ...@@ -3470,7 +3456,7 @@ sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
case CONST_INT: case CONST_INT:
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
{ {
if (INTVAL (x) == 0) if (INTVAL (x) == 0)
*total = 0; *total = 0;
else if (outer_code == AND && and_operand ((x), DImode)) else if (outer_code == AND && and_operand ((x), DImode))
...@@ -3480,15 +3466,15 @@ sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, ...@@ -3480,15 +3466,15 @@ sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
&& CONST_OK_FOR_I10 (INTVAL (x))) && CONST_OK_FOR_I10 (INTVAL (x)))
*total = 0; *total = 0;
else if (CONST_OK_FOR_I16 (INTVAL (x))) else if (CONST_OK_FOR_I16 (INTVAL (x)))
*total = COSTS_N_INSNS (outer_code != SET); *total = COSTS_N_INSNS (outer_code != SET);
else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16)) else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
*total = COSTS_N_INSNS ((outer_code != SET) + 1); *total = COSTS_N_INSNS ((outer_code != SET) + 1);
else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16)) else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
*total = COSTS_N_INSNS ((outer_code != SET) + 2); *total = COSTS_N_INSNS ((outer_code != SET) + 2);
else else
*total = COSTS_N_INSNS ((outer_code != SET) + 3); *total = COSTS_N_INSNS ((outer_code != SET) + 3);
return true; return true;
} }
if (CONST_OK_FOR_I08 (INTVAL (x))) if (CONST_OK_FOR_I08 (INTVAL (x)))
*total = 0; *total = 0;
else if ((outer_code == AND || outer_code == IOR || outer_code == XOR) else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
...@@ -3525,23 +3511,23 @@ sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, ...@@ -3525,23 +3511,23 @@ sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
case LABEL_REF: case LABEL_REF:
case SYMBOL_REF: case SYMBOL_REF:
if (TARGET_SHMEDIA64) if (TARGET_SHMEDIA64)
*total = COSTS_N_INSNS (4); *total = COSTS_N_INSNS (4);
else if (TARGET_SHMEDIA32) else if (TARGET_SHMEDIA32)
*total = COSTS_N_INSNS (2); *total = COSTS_N_INSNS (2);
else else
*total = 5; *total = 5;
return true; return true;
case CONST_DOUBLE: case CONST_DOUBLE:
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
*total = COSTS_N_INSNS (4); *total = COSTS_N_INSNS (4);
/* prepare_cmp_insn will force costly constants int registers before /* prepare_cmp_insn will force costly constants int registers before
the cbranchdi4 pattern can see them, so preserve potentially the cbranchdi4 pattern can see them, so preserve potentially
interesting ones. */ interesting ones. */
else if (outer_code == COMPARE && GET_MODE (x) == DImode) else if (outer_code == COMPARE && GET_MODE (x) == DImode)
*total = 1; *total = 1;
else else
*total = 10; *total = 10;
return true; return true;
case CONST_VECTOR: case CONST_VECTOR:
...@@ -3626,7 +3612,6 @@ sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, ...@@ -3626,7 +3612,6 @@ sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
/* Determine the size of the fundamental move insn that will be used /* Determine the size of the fundamental move insn that will be used
for the specified mode. */ for the specified mode. */
static inline int static inline int
mov_insn_size (enum machine_mode mode, bool consider_sh2a) mov_insn_size (enum machine_mode mode, bool consider_sh2a)
{ {
...@@ -3646,7 +3631,6 @@ mov_insn_size (enum machine_mode mode, bool consider_sh2a) ...@@ -3646,7 +3631,6 @@ mov_insn_size (enum machine_mode mode, bool consider_sh2a)
/* Determine the maximum possible displacement for a move insn for the /* Determine the maximum possible displacement for a move insn for the
specified mode. */ specified mode. */
static int static int
max_mov_insn_displacement (enum machine_mode mode, bool consider_sh2a) max_mov_insn_displacement (enum machine_mode mode, bool consider_sh2a)
{ {
...@@ -3676,7 +3660,6 @@ max_mov_insn_displacement (enum machine_mode mode, bool consider_sh2a) ...@@ -3676,7 +3660,6 @@ max_mov_insn_displacement (enum machine_mode mode, bool consider_sh2a)
/* Determine the alignment mask for a move insn of the /* Determine the alignment mask for a move insn of the
specified mode. */ specified mode. */
static inline int static inline int
mov_insn_alignment_mask (enum machine_mode mode, bool consider_sh2a) mov_insn_alignment_mask (enum machine_mode mode, bool consider_sh2a)
{ {
...@@ -3685,7 +3668,6 @@ mov_insn_alignment_mask (enum machine_mode mode, bool consider_sh2a) ...@@ -3685,7 +3668,6 @@ mov_insn_alignment_mask (enum machine_mode mode, bool consider_sh2a)
} }
/* Return the displacement value of a displacement address. */ /* Return the displacement value of a displacement address. */
static inline HOST_WIDE_INT static inline HOST_WIDE_INT
disp_addr_displacement (rtx x) disp_addr_displacement (rtx x)
{ {
...@@ -3694,7 +3676,6 @@ disp_addr_displacement (rtx x) ...@@ -3694,7 +3676,6 @@ disp_addr_displacement (rtx x)
} }
/* Compute the cost of an address. */ /* Compute the cost of an address. */
static int static int
sh_address_cost (rtx x, enum machine_mode mode, sh_address_cost (rtx x, enum machine_mode mode,
addr_space_t as ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED) addr_space_t as ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED)
...@@ -3749,7 +3730,6 @@ sh_address_cost (rtx x, enum machine_mode mode, ...@@ -3749,7 +3730,6 @@ sh_address_cost (rtx x, enum machine_mode mode,
} }
/* Code to expand a shift. */ /* Code to expand a shift. */
static void static void
gen_ashift (int type, int n, rtx reg) gen_ashift (int type, int n, rtx reg)
{ {
...@@ -3775,7 +3755,7 @@ gen_ashift (int type, int n, rtx reg) ...@@ -3775,7 +3755,7 @@ gen_ashift (int type, int n, rtx reg)
break; break;
case LSHIFTRT: case LSHIFTRT:
if (n == 1) if (n == 1)
emit_insn (gen_shlr (reg, reg)); emit_insn (gen_shlr (reg, reg));
else else
emit_insn (gen_lshrsi3_k (reg, reg, n_rtx)); emit_insn (gen_lshrsi3_k (reg, reg, n_rtx));
break; break;
...@@ -3787,7 +3767,7 @@ gen_ashift (int type, int n, rtx reg) ...@@ -3787,7 +3767,7 @@ gen_ashift (int type, int n, rtx reg)
} }
} }
/* Same for HImode */ /* Code to expand a HImode shift. */
static void static void
gen_ashift_hi (int type, int n, rtx reg) gen_ashift_hi (int type, int n, rtx reg)
{ {
...@@ -3828,7 +3808,6 @@ gen_ashift_hi (int type, int n, rtx reg) ...@@ -3828,7 +3808,6 @@ gen_ashift_hi (int type, int n, rtx reg)
/* Output RTL to split a constant shift into its component SH constant /* Output RTL to split a constant shift into its component SH constant
shift instructions. */ shift instructions. */
void void
gen_shifty_op (int code, rtx *operands) gen_shifty_op (int code, rtx *operands)
{ {
...@@ -3872,9 +3851,8 @@ gen_shifty_op (int code, rtx *operands) ...@@ -3872,9 +3851,8 @@ gen_shifty_op (int code, rtx *operands)
gen_ashift (code, ashl_lshr_seq[value].amount[i], operands[0]); gen_ashift (code, ashl_lshr_seq[value].amount[i], operands[0]);
} }
/* Same as above, but optimized for values where the topmost bits don't /* Same as gen_shifty_op, but optimized for values where the topmost bits
matter. */ don't matter. */
void void
gen_shifty_hi_op (int code, rtx *operands) gen_shifty_hi_op (int code, rtx *operands)
{ {
...@@ -3905,10 +3883,8 @@ gen_shifty_hi_op (int code, rtx *operands) ...@@ -3905,10 +3883,8 @@ gen_shifty_hi_op (int code, rtx *operands)
gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]); gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]);
} }
/* Output RTL for an arithmetic right shift. */ /* Output RTL for an arithmetic right shift.
??? Rewrite to use super-optimizer sequences. */
/* ??? Rewrite to use super-optimizer sequences. */
bool bool
expand_ashiftrt (rtx *operands) expand_ashiftrt (rtx *operands)
{ {
...@@ -4144,7 +4120,6 @@ shl_and_length (rtx insn) ...@@ -4144,7 +4120,6 @@ shl_and_length (rtx insn)
} }
/* This is used in length attribute of the and_shl_scratch instruction. */ /* This is used in length attribute of the and_shl_scratch instruction. */
int int
shl_and_scr_length (rtx insn) shl_and_scr_length (rtx insn)
{ {
...@@ -4158,7 +4133,6 @@ shl_and_scr_length (rtx insn) ...@@ -4158,7 +4133,6 @@ shl_and_scr_length (rtx insn)
/* Generate rtl for instructions for which shl_and_kind advised a particular /* Generate rtl for instructions for which shl_and_kind advised a particular
method of generating them, i.e. returned zero. */ method of generating them, i.e. returned zero. */
bool bool
gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source) gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
{ {
...@@ -4289,7 +4263,6 @@ gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source) ...@@ -4289,7 +4263,6 @@ gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
return 6 for < 8 bit sign extend / left shift. return 6 for < 8 bit sign extend / left shift.
return 7 for < 8 bit sign extend / left shift / single right shift. return 7 for < 8 bit sign extend / left shift / single right shift.
If COSTP is nonzero, assign the calculated cost to *COSTP. */ If COSTP is nonzero, assign the calculated cost to *COSTP. */
int int
shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp) shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
{ {
...@@ -4387,7 +4360,6 @@ shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp) ...@@ -4387,7 +4360,6 @@ shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
/* Function to be used in the length attribute of the instructions /* Function to be used in the length attribute of the instructions
implementing this pattern. */ implementing this pattern. */
int int
shl_sext_length (rtx insn) shl_sext_length (rtx insn)
{ {
...@@ -4402,7 +4374,6 @@ shl_sext_length (rtx insn) ...@@ -4402,7 +4374,6 @@ shl_sext_length (rtx insn)
} }
/* Generate rtl for this pattern */ /* Generate rtl for this pattern */
bool bool
gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source) gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
{ {
...@@ -4523,7 +4494,6 @@ gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source) ...@@ -4523,7 +4494,6 @@ gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
} }
/* Prefix a symbol_ref name with "datalabel". */ /* Prefix a symbol_ref name with "datalabel". */
rtx rtx
gen_datalabel_ref (rtx sym) gen_datalabel_ref (rtx sym)
{ {
...@@ -4643,7 +4613,6 @@ static int max_labelno_before_reorg; ...@@ -4643,7 +4613,6 @@ static int max_labelno_before_reorg;
necessary. */ necessary. */
/* Add a constant to the pool and return its label. */ /* Add a constant to the pool and return its label. */
static rtx static rtx
add_constant (rtx x, enum machine_mode mode, rtx last_value) add_constant (rtx x, enum machine_mode mode, rtx last_value)
{ {
...@@ -4722,7 +4691,6 @@ add_constant (rtx x, enum machine_mode mode, rtx last_value) ...@@ -4722,7 +4691,6 @@ add_constant (rtx x, enum machine_mode mode, rtx last_value)
casesi_worker_2 instruction; We have to emit the operand3 labels from casesi_worker_2 instruction; We have to emit the operand3 labels from
these insns at a 4-byte aligned position. BARRIER is the barrier these insns at a 4-byte aligned position. BARRIER is the barrier
after which we are to place the table. */ after which we are to place the table. */
static void static void
dump_table (rtx start, rtx barrier) dump_table (rtx start, rtx barrier)
{ {
...@@ -4912,7 +4880,6 @@ dump_table (rtx start, rtx barrier) ...@@ -4912,7 +4880,6 @@ dump_table (rtx start, rtx barrier)
/* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
need to fix it if the input value is CONST_OK_FOR_I08. */ need to fix it if the input value is CONST_OK_FOR_I08. */
static bool static bool
broken_move (rtx insn) broken_move (rtx insn)
{ {
...@@ -4936,7 +4903,8 @@ broken_move (rtx insn) ...@@ -4936,7 +4903,8 @@ broken_move (rtx insn)
&& GET_CODE (SET_SRC (pat)) == CONST_DOUBLE && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
&& (fp_zero_operand (SET_SRC (pat)) && (fp_zero_operand (SET_SRC (pat))
|| fp_one_operand (SET_SRC (pat))) || fp_one_operand (SET_SRC (pat)))
/* In general we don't know the current setting of fpscr, so disable fldi. /* In general we don't know the current setting of fpscr, so
disable fldi.
There is an exception if this was a register-register move There is an exception if this was a register-register move
before reload - and hence it was ascertained that we have before reload - and hence it was ascertained that we have
single precision setting - and in a post-reload optimization single precision setting - and in a post-reload optimization
...@@ -4958,6 +4926,7 @@ broken_move (rtx insn) ...@@ -4958,6 +4926,7 @@ broken_move (rtx insn)
return false; return false;
} }
/* Return true if the specified insn is a mova insn. */
static bool static bool
mova_p (rtx insn) mova_p (rtx insn)
{ {
...@@ -5064,7 +5033,6 @@ untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova) ...@@ -5064,7 +5033,6 @@ untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
/* Find the last barrier from insn FROM which is close enough to hold the /* Find the last barrier from insn FROM which is close enough to hold the
constant pool. If we can't find one, then create one near the end of constant pool. If we can't find one, then create one near the end of
the range. */ the range. */
static rtx static rtx
find_barrier (int num_mova, rtx mova, rtx from) find_barrier (int num_mova, rtx mova, rtx from)
{ {
...@@ -5179,10 +5147,10 @@ find_barrier (int num_mova, rtx mova, rtx from) ...@@ -5179,10 +5147,10 @@ find_barrier (int num_mova, rtx mova, rtx from)
mov.l .L8,r12 mov.l .L8,r12
instructions. (plus add r0,r12). instructions. (plus add r0,r12).
Remember if we see one without the other. */ Remember if we see one without the other. */
if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0))) if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0)))
last_got = last_got ? NULL_RTX : from; last_got = last_got ? NULL_RTX : from;
else if (PIC_ADDR_P (src)) else if (PIC_ADDR_P (src))
last_got = last_got ? NULL_RTX : from; last_got = last_got ? NULL_RTX : from;
/* We must explicitly check the mode, because sometimes the /* We must explicitly check the mode, because sometimes the
front end will generate code to load unsigned constants into front end will generate code to load unsigned constants into
...@@ -5442,7 +5410,6 @@ sfunc_uses_reg (rtx insn) ...@@ -5442,7 +5410,6 @@ sfunc_uses_reg (rtx insn)
/* See if the only way in which INSN uses REG is by calling it, or by /* See if the only way in which INSN uses REG is by calling it, or by
setting it while calling it. Set *SET to a SET rtx if the register setting it while calling it. Set *SET to a SET rtx if the register
is set by INSN. */ is set by INSN. */
static bool static bool
noncall_uses_reg (rtx reg, rtx insn, rtx *set) noncall_uses_reg (rtx reg, rtx insn, rtx *set)
{ {
...@@ -5504,7 +5471,7 @@ noncall_uses_reg (rtx reg, rtx insn, rtx *set) ...@@ -5504,7 +5471,7 @@ noncall_uses_reg (rtx reg, rtx insn, rtx *set)
if (reg_mentioned_p (reg, SET_DEST (pattern))) if (reg_mentioned_p (reg, SET_DEST (pattern)))
{ {
/* We don't use rtx_equal_p, because we don't care if the /* We don't use rtx_equal_p, because we don't care if the
mode is different. */ mode is different. */
if (!REG_P (SET_DEST (pattern)) if (!REG_P (SET_DEST (pattern))
|| REGNO (reg) != REGNO (SET_DEST (pattern))) || REGNO (reg) != REGNO (SET_DEST (pattern)))
return true; return true;
...@@ -5603,7 +5570,6 @@ regs_used (rtx x, int is_dest) ...@@ -5603,7 +5570,6 @@ regs_used (rtx x, int is_dest)
pass 1. Pass 2 if a definite blocking insn is needed. pass 1. Pass 2 if a definite blocking insn is needed.
-1 is used internally to avoid deep recursion. -1 is used internally to avoid deep recursion.
If a blocking instruction is made or recognized, return it. */ If a blocking instruction is made or recognized, return it. */
static rtx static rtx
gen_block_redirect (rtx jump, int addr, int need_block) gen_block_redirect (rtx jump, int addr, int need_block)
{ {
...@@ -6019,7 +5985,6 @@ sh_loop_align (rtx label) ...@@ -6019,7 +5985,6 @@ sh_loop_align (rtx label)
/* Do a final pass over the function, just before delayed branch /* Do a final pass over the function, just before delayed branch
scheduling. */ scheduling. */
static void static void
sh_reorg (void) sh_reorg (void)
{ {
...@@ -6104,13 +6069,13 @@ sh_reorg (void) ...@@ -6104,13 +6069,13 @@ sh_reorg (void)
scan = PREV_INSN (scan)) scan = PREV_INSN (scan))
{ {
if (! INSN_P (scan)) if (! INSN_P (scan))
continue; continue;
if (! reg_mentioned_p (reg, scan)) if (! reg_mentioned_p (reg, scan))
continue; continue;
if (noncall_uses_reg (reg, scan, &set)) if (noncall_uses_reg (reg, scan, &set))
break; break;
if (set) if (set)
{ {
...@@ -6125,16 +6090,16 @@ sh_reorg (void) ...@@ -6125,16 +6090,16 @@ sh_reorg (void)
/* The register is set at LINK. */ /* The register is set at LINK. */
/* We can only optimize the function call if the register is /* We can only optimize the function call if the register is
being set to a symbol. In theory, we could sometimes being set to a symbol. In theory, we could sometimes
optimize calls to a constant location, but the assembler optimize calls to a constant location, but the assembler
and linker do not support that at present. */ and linker do not support that at present. */
if (GET_CODE (SET_SRC (set)) != SYMBOL_REF if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
&& GET_CODE (SET_SRC (set)) != LABEL_REF) && GET_CODE (SET_SRC (set)) != LABEL_REF)
continue; continue;
/* Scan forward from LINK to the place where REG dies, and /* Scan forward from LINK to the place where REG dies, and
make sure that the only insns which use REG are make sure that the only insns which use REG are
themselves function calls. */ themselves function calls. */
/* ??? This doesn't work for call targets that were allocated /* ??? This doesn't work for call targets that were allocated
by reload, since there may not be a REG_DEAD note for the by reload, since there may not be a REG_DEAD note for the
...@@ -6159,8 +6124,8 @@ sh_reorg (void) ...@@ -6159,8 +6124,8 @@ sh_reorg (void)
continue; continue;
/* Don't try to trace forward past a JUMP. To optimize /* Don't try to trace forward past a JUMP. To optimize
safely, we would have to check that all the safely, we would have to check that all the
instructions at the jump destination did not use REG. */ instructions at the jump destination did not use REG. */
if (JUMP_P (scan)) if (JUMP_P (scan))
break; break;
...@@ -6178,8 +6143,8 @@ sh_reorg (void) ...@@ -6178,8 +6143,8 @@ sh_reorg (void)
&& (CALL_P (scan) || sfunc_uses_reg (scan))) && (CALL_P (scan) || sfunc_uses_reg (scan)))
{ {
/* There is a function call to this register other /* There is a function call to this register other
than the one we are checking. If we optimize than the one we are checking. If we optimize
this call, we need to rescan again below. */ this call, we need to rescan again below. */
rescan = 1; rescan = 1;
} }
...@@ -6209,15 +6174,15 @@ sh_reorg (void) ...@@ -6209,15 +6174,15 @@ sh_reorg (void)
if (! dies) if (! dies)
{ {
/* Either there was a branch, or some insn used REG /* Either there was a branch, or some insn used REG
other than as a function call address. */ other than as a function call address. */
continue; continue;
} }
/* Create a code label, and put it in a REG_LABEL_OPERAND note /* Create a code label, and put it in a REG_LABEL_OPERAND note
on the insn which sets the register, and on each call insn on the insn which sets the register, and on each call insn
which uses the register. In final_prescan_insn we look for which uses the register. In final_prescan_insn we look for
the REG_LABEL_OPERAND notes, and output the appropriate label the REG_LABEL_OPERAND notes, and output the appropriate label
or pseudo-op. */ or pseudo-op. */
label = gen_label_rtx (); label = gen_label_rtx ();
add_reg_note (link, REG_LABEL_OPERAND, label); add_reg_note (link, REG_LABEL_OPERAND, label);
...@@ -6480,6 +6445,7 @@ sh_reorg (void) ...@@ -6480,6 +6445,7 @@ sh_reorg (void)
mdep_reorg_phase = SH_AFTER_MDEP_REORG; mdep_reorg_phase = SH_AFTER_MDEP_REORG;
} }
/* Return the UID of the insn that follows the specified label. */
int int
get_dest_uid (rtx label, int max_uid) get_dest_uid (rtx label, int max_uid)
{ {
...@@ -6508,7 +6474,6 @@ get_dest_uid (rtx label, int max_uid) ...@@ -6508,7 +6474,6 @@ get_dest_uid (rtx label, int max_uid)
We do this before delay slot scheduling, so that it can take our We do this before delay slot scheduling, so that it can take our
newly created instructions into account. It also allows us to newly created instructions into account. It also allows us to
find branches with common targets more easily. */ find branches with common targets more easily. */
static void static void
split_branches (rtx first) split_branches (rtx first)
{ {
...@@ -6727,13 +6692,12 @@ split_branches (rtx first) ...@@ -6727,13 +6692,12 @@ split_branches (rtx first)
constant pool table stuff. constant pool table stuff.
If relaxing, output the label and pseudo-ops used to link together If relaxing, output the label and pseudo-ops used to link together
calls and the instruction which set the registers. */ calls and the instruction which set the registers.
/* ??? The addresses printed by this routine for insns are nonsense for ??? The addresses printed by this routine for insns are nonsense for
insns which are inside of a sequence where none of the inner insns have insns which are inside of a sequence where none of the inner insns have
variable length. This is because the second pass of shorten_branches variable length. This is because the second pass of shorten_branches
does not bother to update them. */ does not bother to update them. */
void void
final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED, final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
int noperands ATTRIBUTE_UNUSED) int noperands ATTRIBUTE_UNUSED)
...@@ -6778,7 +6742,6 @@ final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED, ...@@ -6778,7 +6742,6 @@ final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
/* Dump out any constants accumulated in the final pass. These will /* Dump out any constants accumulated in the final pass. These will
only be labels. */ only be labels. */
const char * const char *
output_jump_label_table (void) output_jump_label_table (void)
{ {
...@@ -6818,17 +6781,16 @@ output_jump_label_table (void) ...@@ -6818,17 +6781,16 @@ output_jump_label_table (void)
local-n local-n
.. ..
local-1 local-1
local-0 <- fp points here. */ local-0 <- fp points here.
/* Number of bytes pushed for anonymous args, used to pass information Number of bytes pushed for anonymous args, used to pass information
between expand_prologue and expand_epilogue. */ between expand_prologue and expand_epilogue.
/* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
for an epilogue and a negative value means that it's for a sibcall for an epilogue and a negative value means that it's for a sibcall
epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
all the registers that are about to be restored, and hence dead. */ all the registers that are about to be restored, and hence dead. */
static void static void
output_stack_adjust (int size, rtx reg, int epilogue_p, output_stack_adjust (int size, rtx reg, int epilogue_p,
HARD_REG_SET *live_regs_mask, bool frame_p) HARD_REG_SET *live_regs_mask, bool frame_p)
...@@ -6991,6 +6953,8 @@ output_stack_adjust (int size, rtx reg, int epilogue_p, ...@@ -6991,6 +6953,8 @@ output_stack_adjust (int size, rtx reg, int epilogue_p,
} }
} }
/* Emit the specified insn and mark it as frame related.
FIXME: Rename this to emit_frame_insn. */
static rtx static rtx
frame_insn (rtx x) frame_insn (rtx x)
{ {
...@@ -7000,7 +6964,6 @@ frame_insn (rtx x) ...@@ -7000,7 +6964,6 @@ frame_insn (rtx x)
} }
/* Output RTL to push register RN onto the stack. */ /* Output RTL to push register RN onto the stack. */
static rtx static rtx
push (int rn) push (int rn)
{ {
...@@ -7009,8 +6972,8 @@ push (int rn) ...@@ -7009,8 +6972,8 @@ push (int rn)
x = gen_push_fpul (); x = gen_push_fpul ();
else if (rn == FPSCR_REG) else if (rn == FPSCR_REG)
x = gen_push_fpscr (); x = gen_push_fpscr ();
else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD
&& FP_OR_XD_REGISTER_P (rn)) && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn))
{ {
if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1) if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
return NULL_RTX; return NULL_RTX;
...@@ -7027,7 +6990,6 @@ push (int rn) ...@@ -7027,7 +6990,6 @@ push (int rn)
} }
/* Output RTL to pop register RN from the stack. */ /* Output RTL to pop register RN from the stack. */
static void static void
pop (int rn) pop (int rn)
{ {
...@@ -7036,8 +6998,8 @@ pop (int rn) ...@@ -7036,8 +6998,8 @@ pop (int rn)
x = gen_pop_fpul (); x = gen_pop_fpul ();
else if (rn == FPSCR_REG) else if (rn == FPSCR_REG)
x = gen_pop_fpscr (); x = gen_pop_fpscr ();
else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD
&& FP_OR_XD_REGISTER_P (rn)) && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn))
{ {
if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1) if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
return; return;
...@@ -7064,7 +7026,6 @@ pop (int rn) ...@@ -7064,7 +7026,6 @@ pop (int rn)
} }
/* Generate code to push the regs specified in the mask. */ /* Generate code to push the regs specified in the mask. */
static void static void
push_regs (HARD_REG_SET *mask, int interrupt_handler) push_regs (HARD_REG_SET *mask, int interrupt_handler)
{ {
...@@ -7092,16 +7053,16 @@ push_regs (HARD_REG_SET *mask, int interrupt_handler) ...@@ -7092,16 +7053,16 @@ push_regs (HARD_REG_SET *mask, int interrupt_handler)
if (i != PR_REG if (i != PR_REG
&& (i != FPSCR_REG || ! skip_fpscr) && (i != FPSCR_REG || ! skip_fpscr)
&& TEST_HARD_REG_BIT (*mask, i)) && TEST_HARD_REG_BIT (*mask, i))
{ {
/* If the ISR has RESBANK attribute assigned, don't push any of /* If the ISR has RESBANK attribute assigned, don't push any of
the following registers - R0-R14, MACH, MACL and GBR. */ the following registers - R0-R14, MACH, MACL and GBR. */
if (! (sh_cfun_resbank_handler_p () if (! (sh_cfun_resbank_handler_p ()
&& ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG) && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
|| i == MACH_REG || i == MACH_REG
|| i == MACL_REG || i == MACL_REG
|| i == GBR_REG))) || i == GBR_REG)))
push (i); push (i);
} }
} }
/* Push banked registers last to improve delay slot opportunities. */ /* Push banked registers last to improve delay slot opportunities. */
...@@ -7162,7 +7123,6 @@ push_regs (HARD_REG_SET *mask, int interrupt_handler) ...@@ -7162,7 +7123,6 @@ push_regs (HARD_REG_SET *mask, int interrupt_handler)
/* Calculate how much extra space is needed to save all callee-saved /* Calculate how much extra space is needed to save all callee-saved
target registers. target registers.
LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */ LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
static int static int
shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask) shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
{ {
...@@ -7172,7 +7132,7 @@ shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask) ...@@ -7172,7 +7132,7 @@ shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--) for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
if ((! call_really_used_regs[reg] || interrupt_handler) if ((! call_really_used_regs[reg] || interrupt_handler)
&& ! TEST_HARD_REG_BIT (*live_regs_mask, reg)) && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
/* Leave space to save this target register on the stack, /* Leave space to save this target register on the stack,
in case target register allocation wants to use it. */ in case target register allocation wants to use it. */
stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg)); stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
...@@ -7183,7 +7143,6 @@ shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask) ...@@ -7183,7 +7143,6 @@ shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
in case target register allocation wants to use them. REGS_SAVED is in case target register allocation wants to use them. REGS_SAVED is
the space, in bytes, that is already required for register saves. the space, in bytes, that is already required for register saves.
LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */ LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
static int static int
shmedia_reserve_space_for_target_registers_p (int regs_saved, shmedia_reserve_space_for_target_registers_p (int regs_saved,
HARD_REG_SET *live_regs_mask) HARD_REG_SET *live_regs_mask)
...@@ -7196,7 +7155,6 @@ shmedia_reserve_space_for_target_registers_p (int regs_saved, ...@@ -7196,7 +7155,6 @@ shmedia_reserve_space_for_target_registers_p (int regs_saved,
/* Decide how much space to reserve for callee-save target registers /* Decide how much space to reserve for callee-save target registers
in case target register allocation wants to use them. in case target register allocation wants to use them.
LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */ LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
static int static int
shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask) shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
{ {
...@@ -7212,7 +7170,6 @@ shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask) ...@@ -7212,7 +7170,6 @@ shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
If doing a pragma interrupt function, then push all regs used by the If doing a pragma interrupt function, then push all regs used by the
function, and if we call another function (we can tell by looking at PR), function, and if we call another function (we can tell by looking at PR),
make sure that all the regs it clobbers are safe too. */ make sure that all the regs it clobbers are safe too. */
static int static int
calc_live_regs (HARD_REG_SET *live_regs_mask) calc_live_regs (HARD_REG_SET *live_regs_mask)
{ {
...@@ -7234,7 +7191,8 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) ...@@ -7234,7 +7191,8 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
&& df_regs_ever_live_p (FPSCR_REG)) && df_regs_ever_live_p (FPSCR_REG))
target_flags &= ~MASK_FPU_SINGLE; target_flags &= ~MASK_FPU_SINGLE;
/* If we can save a lot of saves by switching to double mode, do that. */ /* If we can save a lot of saves by switching to double mode, do that. */
else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE) else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD
&& TARGET_FPU_SINGLE)
for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2) for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1) if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
&& (! call_really_used_regs[reg] && (! call_really_used_regs[reg]
...@@ -7438,7 +7396,6 @@ typedef struct save_schedule_s ...@@ -7438,7 +7396,6 @@ typedef struct save_schedule_s
use reverse order. Returns the last entry written to (not counting use reverse order. Returns the last entry written to (not counting
the delimiter). OFFSET_BASE is a number to be added to all offset the delimiter). OFFSET_BASE is a number to be added to all offset
entries. */ entries. */
static save_entry * static save_entry *
sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule, sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
int offset_base) int offset_base)
...@@ -7532,6 +7489,7 @@ sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule, ...@@ -7532,6 +7489,7 @@ sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
return entry - 1; return entry - 1;
} }
/* Expand code for the function prologue. */
void void
sh_expand_prologue (void) sh_expand_prologue (void)
{ {
...@@ -7893,6 +7851,7 @@ sh_expand_prologue (void) ...@@ -7893,6 +7851,7 @@ sh_expand_prologue (void)
current_function_static_stack_size = stack_usage; current_function_static_stack_size = stack_usage;
} }
/* Expand code for the function epilogue. */
void void
sh_expand_epilogue (bool sibcall_p) sh_expand_epilogue (bool sibcall_p)
{ {
...@@ -7915,8 +7874,8 @@ sh_expand_epilogue (bool sibcall_p) ...@@ -7915,8 +7874,8 @@ sh_expand_epilogue (bool sibcall_p)
int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask); int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
int total_size; int total_size;
if (d % (STACK_BOUNDARY / BITS_PER_UNIT)) if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
- d % (STACK_BOUNDARY / BITS_PER_UNIT)); - d % (STACK_BOUNDARY / BITS_PER_UNIT));
total_size = d + tregs_space; total_size = d + tregs_space;
total_size += rounded_frame_size (total_size); total_size += rounded_frame_size (total_size);
...@@ -8196,7 +8155,6 @@ sh_expand_epilogue (bool sibcall_p) ...@@ -8196,7 +8155,6 @@ sh_expand_epilogue (bool sibcall_p)
/* Emit code to change the current function's return address to RA. /* Emit code to change the current function's return address to RA.
TEMP is available as a scratch register, if needed. */ TEMP is available as a scratch register, if needed. */
void void
sh_set_return_address (rtx ra, rtx tmp) sh_set_return_address (rtx ra, rtx tmp)
{ {
...@@ -8268,7 +8226,6 @@ sh_set_return_address (rtx ra, rtx tmp) ...@@ -8268,7 +8226,6 @@ sh_set_return_address (rtx ra, rtx tmp)
} }
/* Clear variables at function end. */ /* Clear variables at function end. */
static void static void
sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
HOST_WIDE_INT size ATTRIBUTE_UNUSED) HOST_WIDE_INT size ATTRIBUTE_UNUSED)
...@@ -8424,7 +8381,6 @@ sh_builtin_saveregs (void) ...@@ -8424,7 +8381,6 @@ sh_builtin_saveregs (void)
} }
/* Define the `__builtin_va_list' type for the ABI. */ /* Define the `__builtin_va_list' type for the ABI. */
static tree static tree
sh_build_builtin_va_list (void) sh_build_builtin_va_list (void)
{ {
...@@ -8477,7 +8433,6 @@ sh_build_builtin_va_list (void) ...@@ -8477,7 +8433,6 @@ sh_build_builtin_va_list (void)
} }
/* Implement `va_start' for varargs and stdarg. */ /* Implement `va_start' for varargs and stdarg. */
static void static void
sh_va_start (tree valist, rtx nextarg) sh_va_start (tree valist, rtx nextarg)
{ {
...@@ -8575,8 +8530,8 @@ find_sole_member (tree type) ...@@ -8575,8 +8530,8 @@ find_sole_member (tree type)
} }
return member; return member;
} }
/* Implement `va_arg'. */
/* Implement `va_arg'. */
static tree static tree
sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
gimple_seq *post_p ATTRIBUTE_UNUSED) gimple_seq *post_p ATTRIBUTE_UNUSED)
...@@ -8619,7 +8574,7 @@ sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, ...@@ -8619,7 +8574,7 @@ sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit), next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
valist, f_next_o_limit, NULL_TREE); valist, f_next_o_limit, NULL_TREE);
next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
valist, f_next_fp, NULL_TREE); valist, f_next_fp, NULL_TREE);
next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit), next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
valist, f_next_fp_limit, NULL_TREE); valist, f_next_fp_limit, NULL_TREE);
next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack), next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
...@@ -8793,7 +8748,7 @@ sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, ...@@ -8793,7 +8748,7 @@ sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
} }
/* 64 bit floating points memory transfers are paired single precision loads /* 64 bit floating points memory transfers are paired single precision loads
or store. So DWARF information needs fixing in little endian (unless or store. So DWARF information needs fixing in little endian (unless
PR=SZ=1 in FPSCR). */ PR=SZ=1 in FPSCR). */
rtx rtx
sh_dwarf_register_span (rtx reg) sh_dwarf_register_span (rtx reg)
...@@ -8836,7 +8791,6 @@ sh_promote_prototypes (const_tree type) ...@@ -8836,7 +8791,6 @@ sh_promote_prototypes (const_tree type)
pretend arguments wider than 32-bits that would have been passed in pretend arguments wider than 32-bits that would have been passed in
registers are passed by reference, so that an SHmedia trampoline registers are passed by reference, so that an SHmedia trampoline
loads them into the full 64-bits registers. */ loads them into the full 64-bits registers. */
static int static int
shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode, shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
const_tree type, bool named) const_tree type, bool named)
...@@ -8939,7 +8893,6 @@ sh_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode, ...@@ -8939,7 +8893,6 @@ sh_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
and the rest are pushed. Any arg that starts within the first and the rest are pushed. Any arg that starts within the first
NPARM_REGS words is at least partially passed in a register unless NPARM_REGS words is at least partially passed in a register unless
its data type forbids. */ its data type forbids. */
static rtx static rtx
sh_function_arg (cumulative_args_t ca_v, enum machine_mode mode, sh_function_arg (cumulative_args_t ca_v, enum machine_mode mode,
const_tree type, bool named) const_tree type, bool named)
...@@ -9029,7 +8982,6 @@ sh_function_arg (cumulative_args_t ca_v, enum machine_mode mode, ...@@ -9029,7 +8982,6 @@ sh_function_arg (cumulative_args_t ca_v, enum machine_mode mode,
of mode MODE and data type TYPE. of mode MODE and data type TYPE.
(TYPE is null for libcalls where that information may not be (TYPE is null for libcalls where that information may not be
available.) */ available.) */
static void static void
sh_function_arg_advance (cumulative_args_t ca_v, enum machine_mode mode, sh_function_arg_advance (cumulative_args_t ca_v, enum machine_mode mode,
const_tree type, bool named) const_tree type, bool named)
...@@ -9192,9 +9144,8 @@ sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED) ...@@ -9192,9 +9144,8 @@ sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
For the SH, this is like LIBCALL_VALUE, except that we must change the For the SH, this is like LIBCALL_VALUE, except that we must change the
mode like PROMOTE_MODE does. mode like PROMOTE_MODE does.
??? PROMOTE_MODE is ignored for non-scalar types. The set of types ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
tested here has to be kept in sync with the one in explow.c:promote_mode. tested here has to be kept in sync with the one in
*/ explow.c:promote_mode. */
static rtx static rtx
sh_function_value (const_tree valtype, sh_function_value (const_tree valtype,
const_tree fn_decl_or_type, const_tree fn_decl_or_type,
...@@ -9218,7 +9169,6 @@ sh_function_value (const_tree valtype, ...@@ -9218,7 +9169,6 @@ sh_function_value (const_tree valtype,
} }
/* Worker function for TARGET_LIBCALL_VALUE. */ /* Worker function for TARGET_LIBCALL_VALUE. */
static rtx static rtx
sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
{ {
...@@ -9226,7 +9176,6 @@ sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) ...@@ -9226,7 +9176,6 @@ sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
} }
/* Return true if N is a possible register number of function value. */ /* Return true if N is a possible register number of function value. */
static bool static bool
sh_function_value_regno_p (const unsigned int regno) sh_function_value_regno_p (const unsigned int regno)
{ {
...@@ -9236,7 +9185,6 @@ sh_function_value_regno_p (const unsigned int regno) ...@@ -9236,7 +9185,6 @@ sh_function_value_regno_p (const unsigned int regno)
} }
/* Worker function for TARGET_RETURN_IN_MEMORY. */ /* Worker function for TARGET_RETURN_IN_MEMORY. */
static bool static bool
sh_return_in_memory (const_tree type, const_tree fndecl) sh_return_in_memory (const_tree type, const_tree fndecl)
{ {
...@@ -9299,7 +9247,6 @@ sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v) ...@@ -9299,7 +9247,6 @@ sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v)
/* Define the offset between two registers, one to be eliminated, and /* Define the offset between two registers, one to be eliminated, and
the other its replacement, at the start of a routine. */ the other its replacement, at the start of a routine. */
int int
initial_elimination_offset (int from, int to) initial_elimination_offset (int from, int to)
{ {
...@@ -9333,11 +9280,11 @@ initial_elimination_offset (int from, int to) ...@@ -9333,11 +9280,11 @@ initial_elimination_offset (int from, int to)
if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
return total_saved_regs_space + total_auto_space return total_saved_regs_space + total_auto_space
+ crtl->args.info.byref_regs * 8; + crtl->args.info.byref_regs * 8;
if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
return total_saved_regs_space + total_auto_space return total_saved_regs_space + total_auto_space
+ crtl->args.info.byref_regs * 8; + crtl->args.info.byref_regs * 8;
/* Initial gap between fp and sp is 0. */ /* Initial gap between fp and sp is 0. */
if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
...@@ -9358,15 +9305,15 @@ initial_elimination_offset (int from, int to) ...@@ -9358,15 +9305,15 @@ initial_elimination_offset (int from, int to)
int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG; int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
save_schedule schedule; save_schedule schedule;
save_entry *entry; save_entry *entry;
n += total_auto_space; n += total_auto_space;
/* If it wasn't saved, there's not much we can do. */ /* If it wasn't saved, there's not much we can do. */
if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg)) if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
return n; return n;
target_flags = copy_flags; target_flags = copy_flags;
sh5_schedule_saves (&live_regs_mask, &schedule, n); sh5_schedule_saves (&live_regs_mask, &schedule, n);
for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++) for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
if (entry->reg == pr_reg) if (entry->reg == pr_reg)
...@@ -9386,16 +9333,16 @@ sh_fix_range (const char *const_str) ...@@ -9386,16 +9333,16 @@ sh_fix_range (const char *const_str)
{ {
int i, first, last; int i, first, last;
char *str, *dash, *comma; char *str, *dash, *comma;
/* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
REG2 are either register names or register numbers. The effect REG2 are either register names or register numbers. The effect
of this option is to mark the registers in the range from REG1 to of this option is to mark the registers in the range from REG1 to
REG2 as ``fixed'' so they won't be used by the compiler. */ REG2 as ``fixed'' so they won't be used by the compiler. */
i = strlen (const_str); i = strlen (const_str);
str = (char *) alloca (i + 1); str = (char *) alloca (i + 1);
memcpy (str, const_str, i + 1); memcpy (str, const_str, i + 1);
while (1) while (1)
{ {
dash = strchr (str, '-'); dash = strchr (str, '-');
...@@ -9408,29 +9355,29 @@ sh_fix_range (const char *const_str) ...@@ -9408,29 +9355,29 @@ sh_fix_range (const char *const_str)
comma = strchr (dash + 1, ','); comma = strchr (dash + 1, ',');
if (comma) if (comma)
*comma = '\0'; *comma = '\0';
first = decode_reg_name (str); first = decode_reg_name (str);
if (first < 0) if (first < 0)
{ {
warning (0, "unknown register name: %s", str); warning (0, "unknown register name: %s", str);
return; return;
} }
last = decode_reg_name (dash + 1); last = decode_reg_name (dash + 1);
if (last < 0) if (last < 0)
{ {
warning (0, "unknown register name: %s", dash + 1); warning (0, "unknown register name: %s", dash + 1);
return; return;
} }
*dash = '-'; *dash = '-';
if (first > last) if (first > last)
{ {
warning (0, "%s-%s is an empty range", str, dash + 1); warning (0, "%s-%s is an empty range", str, dash + 1);
return; return;
} }
for (i = first; i <= last; ++i) for (i = first; i <= last; ++i)
fixed_regs[i] = call_used_regs[i] = 1; fixed_regs[i] = call_used_regs[i] = 1;
...@@ -9553,20 +9500,20 @@ sh_insert_attributes (tree node, tree *attributes) ...@@ -9553,20 +9500,20 @@ sh_insert_attributes (tree node, tree *attributes)
/* Handle a 'resbank' attribute. */ /* Handle a 'resbank' attribute. */
static tree static tree
sh_handle_resbank_handler_attribute (tree * node, tree name, sh_handle_resbank_handler_attribute (tree * node, tree name,
tree args ATTRIBUTE_UNUSED, tree args ATTRIBUTE_UNUSED,
int flags ATTRIBUTE_UNUSED, int flags ATTRIBUTE_UNUSED,
bool * no_add_attrs) bool * no_add_attrs)
{ {
if (!TARGET_SH2A) if (!TARGET_SH2A)
{ {
warning (OPT_Wattributes, "%qE attribute is supported only for SH2A", warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
name); name);
*no_add_attrs = true; *no_add_attrs = true;
} }
if (TREE_CODE (*node) != FUNCTION_DECL) if (TREE_CODE (*node) != FUNCTION_DECL)
{ {
warning (OPT_Wattributes, "%qE attribute only applies to functions", warning (OPT_Wattributes, "%qE attribute only applies to functions",
name); name);
*no_add_attrs = true; *no_add_attrs = true;
} }
...@@ -9577,14 +9524,14 @@ sh_handle_resbank_handler_attribute (tree * node, tree name, ...@@ -9577,14 +9524,14 @@ sh_handle_resbank_handler_attribute (tree * node, tree name,
struct attribute_spec.handler. */ struct attribute_spec.handler. */
static tree static tree
sh_handle_interrupt_handler_attribute (tree *node, tree name, sh_handle_interrupt_handler_attribute (tree *node, tree name,
tree args ATTRIBUTE_UNUSED, tree args ATTRIBUTE_UNUSED,
int flags ATTRIBUTE_UNUSED, int flags ATTRIBUTE_UNUSED,
bool *no_add_attrs) bool *no_add_attrs)
{ {
if (TREE_CODE (*node) != FUNCTION_DECL) if (TREE_CODE (*node) != FUNCTION_DECL)
{ {
warning (OPT_Wattributes, "%qE attribute only applies to functions", warning (OPT_Wattributes, "%qE attribute only applies to functions",
name); name);
*no_add_attrs = true; *no_add_attrs = true;
} }
else if (TARGET_SHCOMPACT) else if (TARGET_SHCOMPACT)
...@@ -9600,36 +9547,36 @@ sh_handle_interrupt_handler_attribute (tree *node, tree name, ...@@ -9600,36 +9547,36 @@ sh_handle_interrupt_handler_attribute (tree *node, tree name,
struct attribute_spec.handler. */ struct attribute_spec.handler. */
static tree static tree
sh2a_handle_function_vector_handler_attribute (tree * node, tree name, sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
tree args ATTRIBUTE_UNUSED, tree args ATTRIBUTE_UNUSED,
int flags ATTRIBUTE_UNUSED, int flags ATTRIBUTE_UNUSED,
bool * no_add_attrs) bool * no_add_attrs)
{ {
if (!TARGET_SH2A) if (!TARGET_SH2A)
{ {
warning (OPT_Wattributes, "%qE attribute only applies to SH2A", warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
name); name);
*no_add_attrs = true; *no_add_attrs = true;
} }
else if (TREE_CODE (*node) != FUNCTION_DECL) else if (TREE_CODE (*node) != FUNCTION_DECL)
{ {
warning (OPT_Wattributes, "%qE attribute only applies to functions", warning (OPT_Wattributes, "%qE attribute only applies to functions",
name); name);
*no_add_attrs = true; *no_add_attrs = true;
} }
else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST) else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
{ {
/* The argument must be a constant integer. */ /* The argument must be a constant integer. */
warning (OPT_Wattributes, warning (OPT_Wattributes,
"%qE attribute argument not an integer constant", "%qE attribute argument not an integer constant",
name); name);
*no_add_attrs = true; *no_add_attrs = true;
} }
else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255) else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
{ {
/* The argument value must be between 0 to 255. */ /* The argument value must be between 0 to 255. */
warning (OPT_Wattributes, warning (OPT_Wattributes,
"%qE attribute argument should be between 0 to 255", "%qE attribute argument should be between 0 to 255",
name); name);
*no_add_attrs = true; *no_add_attrs = true;
} }
return NULL_TREE; return NULL_TREE;
...@@ -9666,19 +9613,19 @@ sh2a_get_function_vector_number (rtx x) ...@@ -9666,19 +9613,19 @@ sh2a_get_function_vector_number (rtx x)
t = SYMBOL_REF_DECL (x); t = SYMBOL_REF_DECL (x);
if (TREE_CODE (t) != FUNCTION_DECL) if (TREE_CODE (t) != FUNCTION_DECL)
return 0; return 0;
list = SH_ATTRIBUTES (t); list = SH_ATTRIBUTES (t);
while (list) while (list)
{ {
if (is_attribute_p ("function_vector", TREE_PURPOSE (list))) if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
{ {
num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list))); num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
return num; return num;
} }
list = TREE_CHAIN (list); list = TREE_CHAIN (list);
} }
return 0; return 0;
} }
...@@ -9768,6 +9715,8 @@ sh_cfun_attr_renesas_p (void) ...@@ -9768,6 +9715,8 @@ sh_cfun_attr_renesas_p (void)
return sh_attr_renesas_p (current_function_decl); return sh_attr_renesas_p (current_function_decl);
} }
/* Returns true if the current function has the "interrupt_handler"
attribute set. */
bool bool
sh_cfun_interrupt_handler_p (void) sh_cfun_interrupt_handler_p (void)
{ {
...@@ -9789,28 +9738,26 @@ sh2a_function_vector_p (tree func) ...@@ -9789,28 +9738,26 @@ sh2a_function_vector_p (tree func)
while (list) while (list)
{ {
if (is_attribute_p ("function_vector", TREE_PURPOSE (list))) if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
return true; return true;
list = TREE_CHAIN (list); list = TREE_CHAIN (list);
} }
return false; return false;
} }
/* Returns TRUE if given tree has the "resbank" attribute. */ /* Returns true if given tree has the "resbank" attribute set. */
bool bool
sh_cfun_resbank_handler_p (void) sh_cfun_resbank_handler_p (void)
{ {
return ((lookup_attribute ("resbank", return ((lookup_attribute ("resbank",
DECL_ATTRIBUTES (current_function_decl)) DECL_ATTRIBUTES (current_function_decl))
!= NULL_TREE) != NULL_TREE)
&& (lookup_attribute ("interrupt_handler", && (lookup_attribute ("interrupt_handler",
DECL_ATTRIBUTES (current_function_decl)) DECL_ATTRIBUTES (current_function_decl))
!= NULL_TREE) && TARGET_SH2A); != NULL_TREE) && TARGET_SH2A);
} }
/* Returns true if the current function has a "trap_exit" attribute set. */ /* Returns true if the current function has a "trap_exit" attribute set. */
bool bool
sh_cfun_trap_exit_p (void) sh_cfun_trap_exit_p (void)
{ {
...@@ -9819,7 +9766,6 @@ sh_cfun_trap_exit_p (void) ...@@ -9819,7 +9766,6 @@ sh_cfun_trap_exit_p (void)
} }
/* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */ /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
static const char * static const char *
sh_check_pch_target_flags (int old_flags) sh_check_pch_target_flags (int old_flags)
{ {
...@@ -9838,7 +9784,6 @@ sh_check_pch_target_flags (int old_flags) ...@@ -9838,7 +9784,6 @@ sh_check_pch_target_flags (int old_flags)
/* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx. /* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx.
Used only in general_movsrc_operand. */ Used only in general_movsrc_operand. */
bool bool
system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{ {
...@@ -9853,7 +9798,6 @@ system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) ...@@ -9853,7 +9798,6 @@ system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
} }
/* Returns true if OP is a floating point value with value 0.0. */ /* Returns true if OP is a floating point value with value 0.0. */
bool bool
fp_zero_operand (rtx op) fp_zero_operand (rtx op)
{ {
...@@ -9867,7 +9811,6 @@ fp_zero_operand (rtx op) ...@@ -9867,7 +9811,6 @@ fp_zero_operand (rtx op)
} }
/* Returns true if OP is a floating point value with value 1.0. */ /* Returns true if OP is a floating point value with value 1.0. */
bool bool
fp_one_operand (rtx op) fp_one_operand (rtx op)
{ {
...@@ -9893,7 +9836,7 @@ fldi_ok (void) ...@@ -9893,7 +9836,7 @@ fldi_ok (void)
return true; return true;
} }
/* Return the TLS type for TLS symbols, 0 for otherwise. */ /* Return the TLS type for TLS symbols. */
enum tls_model enum tls_model
tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{ {
...@@ -9903,7 +9846,6 @@ tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) ...@@ -9903,7 +9846,6 @@ tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
} }
/* Return the destination address of a branch. */ /* Return the destination address of a branch. */
static int static int
branch_dest (rtx branch) branch_dest (rtx branch)
{ {
...@@ -10130,7 +10072,6 @@ __complex__ long long f (double d) { if (d == 0) return 2; else return 3; } ...@@ -10130,7 +10072,6 @@ __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
register to a pseudo and using that register, the return value is not register to a pseudo and using that register, the return value is not
live before or after this block, yet we we'll insert our insns right in live before or after this block, yet we we'll insert our insns right in
the middle. */ the middle. */
static rtx static rtx
get_free_reg (HARD_REG_SET regs_live) get_free_reg (HARD_REG_SET regs_live)
{ {
...@@ -10257,7 +10198,6 @@ sh_insn_length_adjustment (rtx insn) ...@@ -10257,7 +10198,6 @@ sh_insn_length_adjustment (rtx insn)
/* Return TRUE for a valid displacement for the REG+disp addressing /* Return TRUE for a valid displacement for the REG+disp addressing
with MODE. */ with MODE. */
bool bool
sh_legitimate_index_p (enum machine_mode mode, rtx op, bool consider_sh2a, sh_legitimate_index_p (enum machine_mode mode, rtx op, bool consider_sh2a,
bool allow_zero) bool allow_zero)
...@@ -10307,7 +10247,6 @@ sh_legitimate_index_p (enum machine_mode mode, rtx op, bool consider_sh2a, ...@@ -10307,7 +10247,6 @@ sh_legitimate_index_p (enum machine_mode mode, rtx op, bool consider_sh2a,
--REG --REG
GBR GBR
GBR+disp */ GBR+disp */
static bool static bool
sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
{ {
...@@ -10453,7 +10392,6 @@ legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, ...@@ -10453,7 +10392,6 @@ legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
does not look at other present displacement addressings around it. does not look at other present displacement addressings around it.
In some cases this can create more base address adjustments than would In some cases this can create more base address adjustments than would
actually be necessary. */ actually be necessary. */
struct disp_adjust struct disp_adjust
{ {
rtx offset_adjust; rtx offset_adjust;
...@@ -10499,7 +10437,6 @@ sh_find_mov_disp_adjust (enum machine_mode mode, HOST_WIDE_INT offset) ...@@ -10499,7 +10437,6 @@ sh_find_mov_disp_adjust (enum machine_mode mode, HOST_WIDE_INT offset)
/* Try to modify an illegitimate address and make it legitimate. /* Try to modify an illegitimate address and make it legitimate.
If we find one, return the new, valid address. If we find one, return the new, valid address.
Otherwise, return the original address. */ Otherwise, return the original address. */
static rtx static rtx
sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode) sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
{ {
...@@ -10535,7 +10472,6 @@ sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode) ...@@ -10535,7 +10472,6 @@ sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
a valid memory address for an operand of mode MODE. a valid memory address for an operand of mode MODE.
Like for sh_legitimize_address, for the SH we try to get a normal form Like for sh_legitimize_address, for the SH we try to get a normal form
of the address. That will allow inheritance of the address reloads. */ of the address. That will allow inheritance of the address reloads. */
bool bool
sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum, sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum,
int itype) int itype)
...@@ -10611,7 +10547,6 @@ sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum, ...@@ -10611,7 +10547,6 @@ sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum,
/* In the name of slightly smaller debug output, and to cater to /* In the name of slightly smaller debug output, and to cater to
general assembler lossage, recognize various UNSPEC sequences general assembler lossage, recognize various UNSPEC sequences
and turn them back into a direct symbol reference. */ and turn them back into a direct symbol reference. */
static rtx static rtx
sh_delegitimize_address (rtx orig_x) sh_delegitimize_address (rtx orig_x)
{ {
...@@ -10766,7 +10701,6 @@ sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, ...@@ -10766,7 +10701,6 @@ sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
/* Interrupt functions can only use registers that have already been /* Interrupt functions can only use registers that have already been
saved by the prologue, even if they would normally be saved by the prologue, even if they would normally be
call-clobbered. */ call-clobbered. */
if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg)) if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
return false; return false;
...@@ -11235,7 +11169,6 @@ sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED, ...@@ -11235,7 +11169,6 @@ sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
CURR_REGMODE_PRESSURE (SImode) = 0; CURR_REGMODE_PRESSURE (SImode) = 0;
CURR_REGMODE_PRESSURE (SFmode) = 0; CURR_REGMODE_PRESSURE (SFmode) = 0;
} }
/* Cleanup. */ /* Cleanup. */
...@@ -11445,7 +11378,6 @@ sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED) ...@@ -11445,7 +11378,6 @@ sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
/* Emit RTL insns to initialize the variable parts of a trampoline. /* Emit RTL insns to initialize the variable parts of a trampoline.
FNADDR is an RTX for the address of the function's pure code. FNADDR is an RTX for the address of the function's pure code.
CXT is an RTX for the static chain value for the function. */ CXT is an RTX for the static chain value for the function. */
static void static void
sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt) sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
{ {
...@@ -11463,8 +11395,8 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt) ...@@ -11463,8 +11395,8 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
/* The following trampoline works within a +- 128 KB range for cxt: /* The following trampoline works within a +- 128 KB range for cxt:
ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0; ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
gettr tr1,r1; blink tr0,r63 */ gettr tr1,r1; blink tr0,r63 */
/* Address rounding makes it hard to compute the exact bounds of the /* Address rounding makes it hard to compute the exact bounds of the
offset for this trampoline, but we have a rather generous offset offset for this trampoline, but we have a rather generous offset
range, so frame_offset should do fine as an upper bound. */ range, so frame_offset should do fine as an upper bound. */
...@@ -11597,7 +11529,6 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt) ...@@ -11597,7 +11529,6 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
} }
/* On SH5, trampolines are SHmedia code, so add 1 to the address. */ /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
static rtx static rtx
sh_trampoline_adjust_address (rtx tramp) sh_trampoline_adjust_address (rtx tramp)
{ {
...@@ -11994,7 +11925,6 @@ sh_dwarf_calling_convention (const_tree func) ...@@ -11994,7 +11925,6 @@ sh_dwarf_calling_convention (const_tree func)
} }
/* Returns the sh builtin decl for CODE. */ /* Returns the sh builtin decl for CODE. */
static tree static tree
sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
{ {
...@@ -12012,7 +11942,6 @@ sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) ...@@ -12012,7 +11942,6 @@ sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
(and in mode MODE if that's convenient). (and in mode MODE if that's convenient).
SUBTARGET may be used as the target for computing one of EXP's operands. SUBTARGET may be used as the target for computing one of EXP's operands.
IGNORE is nonzero if the value is to be ignored. */ IGNORE is nonzero if the value is to be ignored. */
static rtx static rtx
sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
enum machine_mode mode ATTRIBUTE_UNUSED, int ignore) enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
...@@ -12129,7 +12058,6 @@ sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2) ...@@ -12129,7 +12058,6 @@ sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
We want to allow TImode FP regs so that when V4SFmode is loaded as TImode, We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
it won't be ferried through GP registers first. */ it won't be ferried through GP registers first. */
bool bool
sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
{ {
...@@ -12250,7 +12178,6 @@ sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to, ...@@ -12250,7 +12178,6 @@ sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
/* Return true if registers in machine mode MODE will likely be /* Return true if registers in machine mode MODE will likely be
allocated to registers in small register classes. */ allocated to registers in small register classes. */
bool bool
sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED) sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
{ {
...@@ -12259,7 +12186,6 @@ sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED) ...@@ -12259,7 +12186,6 @@ sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
/* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
that label is used. */ that label is used. */
void void
sh_mark_label (rtx address, int nuses) sh_mark_label (rtx address, int nuses)
{ {
...@@ -12277,12 +12203,11 @@ sh_mark_label (rtx address, int nuses) ...@@ -12277,12 +12203,11 @@ sh_mark_label (rtx address, int nuses)
} }
/* Compute extra cost of moving data between one register class /* Compute extra cost of moving data between one register class
and another. */ and another.
/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
uses this information. Hence, the general register <-> floating point uses this information. Hence, the general register <-> floating point
register information here is not used for SFmode. */ register information here is not used for SFmode. */
static int static int
sh_register_move_cost (enum machine_mode mode, sh_register_move_cost (enum machine_mode mode,
reg_class_t srcclass, reg_class_t dstclass) reg_class_t srcclass, reg_class_t dstclass)
...@@ -12479,7 +12404,7 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, ...@@ -12479,7 +12404,7 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
/* scratch0 != scratch1, and we have indexed loads. Get better /* scratch0 != scratch1, and we have indexed loads. Get better
schedule by loading the offset into r1 and using an indexed schedule by loading the offset into r1 and using an indexed
load - then the load of r1 can issue before the load from load - then the load of r1 can issue before the load from
(this_rtx + delta) finishes. */ (this_rtx + delta) finishes. */
emit_move_insn (scratch1, GEN_INT (vcall_offset)); emit_move_insn (scratch1, GEN_INT (vcall_offset));
offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1); offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
} }
...@@ -12589,7 +12514,7 @@ function_symbol (rtx target, const char *name, enum sh_function_kind kind) ...@@ -12589,7 +12514,7 @@ function_symbol (rtx target, const char *name, enum sh_function_kind kind)
case SFUNC_STATIC: case SFUNC_STATIC:
{ {
/* ??? To allow cse to work, we use GOTOFF relocations. /* ??? To allow cse to work, we use GOTOFF relocations.
we could add combiner patterns to transform this into We could add combiner patterns to transform this into
straight pc-relative calls with sym2PIC / bsrf when straight pc-relative calls with sym2PIC / bsrf when
label load and function call are still 1:1 and in the label load and function call are still 1:1 and in the
same basic block during combine. */ same basic block during combine. */
...@@ -12767,13 +12692,12 @@ sh_fsca_int2sf (void) ...@@ -12767,13 +12692,12 @@ sh_fsca_int2sf (void)
} }
/* Initialize the CUMULATIVE_ARGS structure. */ /* Initialize the CUMULATIVE_ARGS structure. */
void void
sh_init_cumulative_args (CUMULATIVE_ARGS * pcum, sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
tree fntype, tree fntype,
rtx libname ATTRIBUTE_UNUSED, rtx libname ATTRIBUTE_UNUSED,
tree fndecl, tree fndecl,
signed int n_named_args, signed int n_named_args,
enum machine_mode mode) enum machine_mode mode)
{ {
pcum->arg_count [(int) SH_ARG_FLOAT] = 0; pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
...@@ -12851,7 +12775,6 @@ sh_init_cumulative_args (CUMULATIVE_ARGS * pcum, ...@@ -12851,7 +12775,6 @@ sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
If MODIFY is zero, don't modify any rtl in place, If MODIFY is zero, don't modify any rtl in place,
just return zero or nonzero for failure / success. */ just return zero or nonzero for failure / success. */
rtx rtx
replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify) replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
{ {
...@@ -13002,7 +12925,7 @@ sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext) ...@@ -13002,7 +12925,7 @@ sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
return gen_rtx_fmt_e (code, mode, x); return gen_rtx_fmt_e (code, mode, x);
} }
/* called via for_each_rtx after reload, to clean up truncates of /* Called via for_each_rtx after reload, to clean up truncates of
registers that span multiple actual hard registers. */ registers that span multiple actual hard registers. */
int int
shmedia_cleanup_truncate (rtx *p, void *n_changes) shmedia_cleanup_truncate (rtx *p, void *n_changes)
...@@ -13026,9 +12949,9 @@ shmedia_cleanup_truncate (rtx *p, void *n_changes) ...@@ -13026,9 +12949,9 @@ shmedia_cleanup_truncate (rtx *p, void *n_changes)
/* Load and store depend on the highpart of the address. However, /* Load and store depend on the highpart of the address. However,
set_attr_alternative does not give well-defined results before reload, set_attr_alternative does not give well-defined results before reload,
so we must look at the rtl ourselves to see if any of the feeding so we must look at the rtl ourselves to see if any of the feeding
registers is used in a memref. */ registers is used in a memref.
/* Called by sh_contains_memref_p via for_each_rtx. */ Called by sh_contains_memref_p via for_each_rtx. */
static int static int
sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED) sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
{ {
...@@ -13105,7 +13028,6 @@ shmedia_prepare_call_address (rtx fnaddr, int is_sibcall) ...@@ -13105,7 +13028,6 @@ shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
} }
/* Implement TARGET_PREFERRED_RELOAD_CLASS. */ /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
static reg_class_t static reg_class_t
sh_preferred_reload_class (rtx x, reg_class_t rclass) sh_preferred_reload_class (rtx x, reg_class_t rclass)
{ {
...@@ -13120,7 +13042,6 @@ sh_preferred_reload_class (rtx x, reg_class_t rclass) ...@@ -13120,7 +13042,6 @@ sh_preferred_reload_class (rtx x, reg_class_t rclass)
} }
/* Implement TARGET_SECONDARY_RELOAD. */ /* Implement TARGET_SECONDARY_RELOAD. */
static reg_class_t static reg_class_t
sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri) enum machine_mode mode, secondary_reload_info *sri)
...@@ -13161,11 +13082,10 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, ...@@ -13161,11 +13082,10 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
abort (); abort ();
} }
if (rclass == FPUL_REGS if (rclass == FPUL_REGS
&& ((REG_P (x) && ((REG_P (x) && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
&& (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG || REGNO (x) == T_REG))
|| REGNO (x) == T_REG)) || GET_CODE (x) == PLUS))
|| GET_CODE (x) == PLUS)) return GENERAL_REGS;
return GENERAL_REGS;
if (rclass == FPUL_REGS && immediate_operand (x, mode)) if (rclass == FPUL_REGS && immediate_operand (x, mode))
{ {
if (satisfies_constraint_I08 (x) || fp_zero_operand (x)) if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
...@@ -13176,25 +13096,25 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, ...@@ -13176,25 +13096,25 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
return NO_REGS; return NO_REGS;
} }
if (rclass == FPSCR_REGS if (rclass == FPSCR_REGS
&& ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER) && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
|| (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS))) || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
return GENERAL_REGS; return GENERAL_REGS;
if (REGCLASS_HAS_FP_REG (rclass) if (REGCLASS_HAS_FP_REG (rclass)
&& TARGET_SHMEDIA && TARGET_SHMEDIA
&& immediate_operand (x, mode) && immediate_operand (x, mode)
&& x != CONST0_RTX (GET_MODE (x)) && x != CONST0_RTX (GET_MODE (x))
&& GET_MODE (x) != V4SFmode) && GET_MODE (x) != V4SFmode)
return GENERAL_REGS; return GENERAL_REGS;
if ((mode == QImode || mode == HImode) if ((mode == QImode || mode == HImode)
&& TARGET_SHMEDIA && inqhi_operand (x, mode)) && TARGET_SHMEDIA && inqhi_operand (x, mode))
{ {
sri->icode = ((mode == QImode) sri->icode = ((mode == QImode)
? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi); ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
return NO_REGS; return NO_REGS;
} }
if (TARGET_SHMEDIA && rclass == GENERAL_REGS if (TARGET_SHMEDIA && rclass == GENERAL_REGS
&& (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x))) && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
return TARGET_REGS; return TARGET_REGS;
} /* end of input-only processing. */ } /* end of input-only processing. */
if (((REGCLASS_HAS_FP_REG (rclass) if (((REGCLASS_HAS_FP_REG (rclass)
...@@ -13210,12 +13130,12 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, ...@@ -13210,12 +13130,12 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
return FPUL_REGS; return FPUL_REGS;
if ((rclass == FPUL_REGS if ((rclass == FPUL_REGS
|| (REGCLASS_HAS_FP_REG (rclass) || (REGCLASS_HAS_FP_REG (rclass)
&& ! TARGET_SHMEDIA && mode == SImode)) && ! TARGET_SHMEDIA && mode == SImode))
&& (MEM_P (x) && (MEM_P (x)
|| (REG_P (x) || (REG_P (x)
&& (REGNO (x) >= FIRST_PSEUDO_REGISTER && (REGNO (x) >= FIRST_PSEUDO_REGISTER
|| REGNO (x) == T_REG || REGNO (x) == T_REG
|| system_reg_operand (x, VOIDmode))))) || system_reg_operand (x, VOIDmode)))))
{ {
if (rclass == FPUL_REGS) if (rclass == FPUL_REGS)
return GENERAL_REGS; return GENERAL_REGS;
...@@ -13315,7 +13235,6 @@ sh_conditional_register_usage (void) ...@@ -13315,7 +13235,6 @@ sh_conditional_register_usage (void)
/* Implement TARGET_LEGITIMATE_CONSTANT_P /* Implement TARGET_LEGITIMATE_CONSTANT_P
can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */ can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
static bool static bool
sh_legitimate_constant_p (enum machine_mode mode, rtx x) sh_legitimate_constant_p (enum machine_mode mode, rtx x)
{ {
...@@ -13339,7 +13258,6 @@ sh_init_sync_libfuncs (void) ...@@ -13339,7 +13258,6 @@ sh_init_sync_libfuncs (void)
/* Return true if it is appropriate to emit `ret' instructions in the /* Return true if it is appropriate to emit `ret' instructions in the
body of a function. */ body of a function. */
bool bool
sh_can_use_simple_return_p (void) sh_can_use_simple_return_p (void)
{ {
......
gcc/config/sh/sh.h
...@@ -129,35 +129,35 @@ extern int code_for_indirect_jump_scratch; ...@@ -129,35 +129,35 @@ extern int code_for_indirect_jump_scratch;
#define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP) #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
#define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE) #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
#define SELECT_SH1 (MASK_SH1) #define SELECT_SH1 (MASK_SH1)
#define SELECT_SH2 (MASK_SH2 | SELECT_SH1) #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
#define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \ #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
| MASK_FPU_SINGLE) | MASK_FPU_SINGLE)
#define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \ #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
| MASK_HARD_SH2A_DOUBLE \ | MASK_HARD_SH2A_DOUBLE \
| MASK_SH2 | MASK_SH1) | MASK_SH2 | MASK_SH1)
#define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1) #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
#define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \ #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
| MASK_SH1 | MASK_FPU_SINGLE) | MASK_SH1 | MASK_FPU_SINGLE)
#define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \ #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
| MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \ | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
| MASK_SH2 | MASK_SH1) | MASK_SH2 | MASK_SH1)
#define SELECT_SH3 (MASK_SH3 | SELECT_SH2) #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
#define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3) #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
#define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3) #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
#define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E) #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
#define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \ #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
| SELECT_SH3) | SELECT_SH3)
#define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4) #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
#define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU) #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4) #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
#define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4) #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
#define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5) #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
#define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E) #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E) #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
#define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E) #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3) #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
#if SUPPORT_SH1 #if SUPPORT_SH1
...@@ -404,7 +404,6 @@ extern enum sh_divide_strategy_e sh_div_strategy; ...@@ -404,7 +404,6 @@ extern enum sh_divide_strategy_e sh_div_strategy;
/* Define this if most significant bit is lowest numbered /* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields. */ in instructions that operate on numbered bit-fields. */
#define BITS_BIG_ENDIAN 0 #define BITS_BIG_ENDIAN 0
/* Define this if most significant byte of a word is the lowest numbered. */ /* Define this if most significant byte of a word is the lowest numbered. */
...@@ -537,15 +536,15 @@ extern enum sh_divide_strategy_e sh_div_strategy; ...@@ -537,15 +536,15 @@ extern enum sh_divide_strategy_e sh_div_strategy;
/* Register allocation for the Renesas calling convention: /* Register allocation for the Renesas calling convention:
r0 arg return r0 arg return
r1..r3 scratch r1..r3 scratch
r4..r7 args in r4..r7 args in
r8..r13 call saved r8..r13 call saved
r14 frame pointer/call saved r14 frame pointer/call saved
r15 stack pointer r15 stack pointer
ap arg pointer (doesn't really exist, always eliminated) ap arg pointer (doesn't really exist, always eliminated)
pr subroutine return address pr subroutine return address
t t bit t t bit
mach multiply/accumulate result, high part mach multiply/accumulate result, high part
macl multiply/accumulate result, low part. macl multiply/accumulate result, low part.
fpul fp/int communication register fpul fp/int communication register
...@@ -559,7 +558,7 @@ extern enum sh_divide_strategy_e sh_div_strategy; ...@@ -559,7 +558,7 @@ extern enum sh_divide_strategy_e sh_div_strategy;
extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1]; extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
#define SH_REGISTER_NAMES_INITIALIZER \ #define SH_REGISTER_NAMES_INITIALIZER \
{ \ { \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
...@@ -661,12 +660,11 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -661,12 +660,11 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
#define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1)) #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
/* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
#define FIRST_BANKED_REG R0_REG #define FIRST_BANKED_REG R0_REG
#define LAST_BANKED_REG R7_REG #define LAST_BANKED_REG R7_REG
#define BANKED_REGISTER_P(REGNO) \ #define BANKED_REGISTER_P(REGNO) \
IN_RANGE ((REGNO), \ IN_RANGE ((REGNO), \
(unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \ (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
(unsigned HOST_WIDE_INT) LAST_BANKED_REG) (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
...@@ -676,7 +674,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -676,7 +674,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
(unsigned HOST_WIDE_INT) LAST_GENERAL_REG) (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
#define GENERAL_OR_AP_REGISTER_P(REGNO) \ #define GENERAL_OR_AP_REGISTER_P(REGNO) \
(GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \ (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
|| ((REGNO) == FRAME_POINTER_REGNUM)) || ((REGNO) == FRAME_POINTER_REGNUM))
#define FP_REGISTER_P(REGNO) \ #define FP_REGISTER_P(REGNO) \
...@@ -730,9 +728,8 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -730,9 +728,8 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
Mach register is fixed 'cause it's only 10 bits wide for SH1. Mach register is fixed 'cause it's only 10 bits wide for SH1.
It is 32 bits wide for SH2. */ It is 32 bits wide for SH2. */
#define FIXED_REGISTERS \
#define FIXED_REGISTERS \ { \
{ \
/* Regular registers. */ \ /* Regular registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, \ 0, 0, 0, 0, 0, 0, 0, 1, \
...@@ -770,9 +767,8 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -770,9 +767,8 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
The latter must include the registers where values are returned The latter must include the registers where values are returned
and the register where structure-value addresses are passed. and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like. */ Aside from that, you can include as many other registers as you like. */
#define CALL_USED_REGISTERS \
#define CALL_USED_REGISTERS \ { \
{ \
/* Regular registers. */ \ /* Regular registers. */ \
1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \
/* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
...@@ -817,7 +813,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -817,7 +813,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
(TARGET_SHMEDIA32 \ (TARGET_SHMEDIA32 \
&& GET_MODE_SIZE (MODE) > 4 \ && GET_MODE_SIZE (MODE) > 4 \
&& (((REGNO) >= FIRST_GENERAL_REG + 10 \ && (((REGNO) >= FIRST_GENERAL_REG + 10 \
&& (REGNO) <= FIRST_GENERAL_REG + 15) \ && (REGNO) <= FIRST_GENERAL_REG + 15) \
|| TARGET_REGISTER_P (REGNO) \ || TARGET_REGISTER_P (REGNO) \
|| (REGNO) == PR_MEDIA_REG)) || (REGNO) == PR_MEDIA_REG))
...@@ -827,7 +823,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -827,7 +823,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
but can be less for certain modes in special long registers. but can be less for certain modes in special long registers.
On the SH all but the XD regs are UNITS_PER_WORD bits wide. */ On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
#define HARD_REGNO_NREGS(REGNO, MODE) \ #define HARD_REGNO_NREGS(REGNO, MODE) \
(XD_REGISTER_P (REGNO) \ (XD_REGISTER_P (REGNO) \
? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \ ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
...@@ -836,8 +831,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -836,8 +831,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
sh_hard_regno_mode_ok ((REGNO), (MODE)) sh_hard_regno_mode_ok ((REGNO), (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers /* Value is 1 if it is a good idea to tie two pseudo registers
...@@ -847,7 +841,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -847,7 +841,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
That's the case for xd registers: we don't hold SFmode values in That's the case for xd registers: we don't hold SFmode values in
them, so we can't tie an SFmode pseudos with one in another them, so we can't tie an SFmode pseudos with one in another
floating-point mode. */ floating-point mode. */
#define MODES_TIEABLE_P(MODE1, MODE2) \ #define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) \ ((MODE1) == (MODE2) \
|| (TARGET_SHMEDIA \ || (TARGET_SHMEDIA \
...@@ -860,7 +853,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -860,7 +853,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
/* A C expression that is nonzero if hard register NEW_REG can be /* A C expression that is nonzero if hard register NEW_REG can be
considered for use as a rename register for OLD_REG register */ considered for use as a rename register for OLD_REG register */
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
sh_hard_regno_rename_ok (OLD_REG, NEW_REG) sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
...@@ -896,14 +888,14 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -896,14 +888,14 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
pointer register. Secondly, the argument pointer register can always be pointer register. Secondly, the argument pointer register can always be
eliminated; it is replaced with either the stack or frame pointer. eliminated; it is replaced with either the stack or frame pointer.
Third, there is the return address pointer, which can also be replaced Third, there is the return address pointer, which can also be replaced
with either the stack or the frame pointer. */ with either the stack or the frame pointer.
/* This is an array of structures. Each structure initializes one pair This is an array of structures. Each structure initializes one pair
of eliminable registers. The "from" register number is given first, of eliminable registers. The "from" register number is given first,
followed by "to". Eliminations of the same "from" register are listed followed by "to". Eliminations of the same "from" register are listed
in order of preference. */ in order of preference.
/* If you add any registers here that are not actually hard registers, If you add any registers here that are not actually hard registers,
and that have any alternative of elimination that doesn't always and that have any alternative of elimination that doesn't always
apply, you need to amend calc_live_regs to exclude it, because apply, you need to amend calc_live_regs to exclude it, because
reload spills all eliminable registers where it sees an reload spills all eliminable registers where it sees an
...@@ -911,7 +903,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -911,7 +903,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
If you add any hard registers that can be eliminated in different If you add any hard registers that can be eliminated in different
ways, you have to patch reload to spill them only when all alternatives ways, you have to patch reload to spill them only when all alternatives
of elimination fail. */ of elimination fail. */
#define ELIMINABLE_REGS \ #define ELIMINABLE_REGS \
{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
...@@ -923,7 +914,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -923,7 +914,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
/* Define the offset between two registers, one to be eliminated, and the other /* Define the offset between two registers, one to be eliminated, and the other
its replacement, at the start of a routine. */ its replacement, at the start of a routine. */
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
OFFSET = initial_elimination_offset ((FROM), (TO)) OFFSET = initial_elimination_offset ((FROM), (TO))
...@@ -936,7 +926,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -936,7 +926,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
/* Don't default to pcc-struct-return, because we have already specified /* Don't default to pcc-struct-return, because we have already specified
exactly how to return structures in the TARGET_RETURN_IN_MEMORY exactly how to return structures in the TARGET_RETURN_IN_MEMORY
target hook. */ target hook. */
#define DEFAULT_PCC_STRUCT_RETURN 0 #define DEFAULT_PCC_STRUCT_RETURN 0
#define SHMEDIA_REGS_STACK_ADJUST() \ #define SHMEDIA_REGS_STACK_ADJUST() \
...@@ -964,13 +953,14 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -964,13 +953,14 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
in a smaller-numbered class. in a smaller-numbered class.
For any two classes, it is very desirable that there be another For any two classes, it is very desirable that there be another
class that represents their union. */ class that represents their union.
/* The SH has two sorts of general registers, R0 and the rest. R0 can The SH has two sorts of general registers, R0 and the rest. R0 can
be used as the destination of some of the arithmetic ops. There are be used as the destination of some of the arithmetic ops. There are
also some special purpose registers; the T bit register, the also some special purpose registers; the T bit register, the
Procedure Return Register and the Multiply Accumulate Registers. */ Procedure Return Register and the Multiply Accumulate Registers.
/* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
reg_class_subunion. We don't want to have an actual union class reg_class_subunion. We don't want to have an actual union class
of these, because it would only be used when both classes are calculated of these, because it would only be used when both classes are calculated
to give the same cost, but there is only one FPUL register. to give the same cost, but there is only one FPUL register.
...@@ -978,7 +968,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -978,7 +968,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
applying to the actual instruction alternative considered. E.g., the applying to the actual instruction alternative considered. E.g., the
y/r alternative of movsi_ie is considered to have no more cost that y/r alternative of movsi_ie is considered to have no more cost that
the r/r alternative, which is patently untrue. */ the r/r alternative, which is patently untrue. */
enum reg_class enum reg_class
{ {
NO_REGS, NO_REGS,
...@@ -1030,7 +1019,6 @@ enum reg_class ...@@ -1030,7 +1019,6 @@ enum reg_class
/* Define which registers fit in which classes. /* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */ of length N_REG_CLASSES. */
#define REG_CLASS_CONTENTS \ #define REG_CLASS_CONTENTS \
{ \ { \
/* NO_REGS: */ \ /* NO_REGS: */ \
...@@ -1055,7 +1043,7 @@ enum reg_class ...@@ -1055,7 +1043,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
/* FP_REGS: */ \ /* FP_REGS: */ \
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
/* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \ /* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
/* DF_REGS: */ \ /* DF_REGS: */ \
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
...@@ -1075,7 +1063,6 @@ enum reg_class ...@@ -1075,7 +1063,6 @@ enum reg_class
Return the class number of the smallest class containing Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression reg number REGNO. This could be a conditional expression
or could index an array. */ or could index an array. */
extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
...@@ -1155,23 +1142,22 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1155,23 +1142,22 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* If defined, gives a class of registers that cannot be used as the /* If defined, gives a class of registers that cannot be used as the
operand of a SUBREG that changes the mode of the object illegally. */ operand of a SUBREG that changes the mode of the object illegally.
/* ??? We need to renumber the internal numbers for the frnn registers ??? We need to renumber the internal numbers for the frnn registers
when in little endian in order to allow mode size changes. */ when in little endian in order to allow mode size changes. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
sh_cannot_change_mode_class (FROM, TO, CLASS) sh_cannot_change_mode_class (FROM, TO, CLASS)
/* Stack layout; function entry, exit and calling. */ /* Stack layout; function entry, exit and calling. */
/* Define the number of registers that can hold parameters. /* Define the number of registers that can hold parameters.
These macros are used only in other macro definitions below. */ These macros are used only in other macro definitions below. */
#define NPARM_REGS(MODE) \ #define NPARM_REGS(MODE) \
(TARGET_FPU_ANY && (MODE) == SFmode \ (TARGET_FPU_ANY && (MODE) == SFmode \
? (TARGET_SH5 ? 12 : 8) \ ? (TARGET_SH5 ? 12 : 8) \
: (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ : (TARGET_SH4 || TARGET_SH2A_DOUBLE) \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
? (TARGET_SH5 ? 12 : 8) \ ? (TARGET_SH5 ? 12 : 8) \
: (TARGET_SH5 ? 8 : 4)) : (TARGET_SH5 ? 8 : 4))
...@@ -1215,9 +1201,9 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1215,9 +1201,9 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
/* Some subroutine macros specific to this machine. */ /* Some subroutine macros specific to this machine. */
#define BASE_RETURN_VALUE_REG(MODE) \ #define BASE_RETURN_VALUE_REG(MODE) \
((TARGET_FPU_ANY && ((MODE) == SFmode)) \ ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
? FIRST_FP_RET_REG \ ? FIRST_FP_RET_REG \
: TARGET_FPU_ANY && (MODE) == SCmode \ : TARGET_FPU_ANY && (MODE) == SCmode \
? FIRST_FP_RET_REG \ ? FIRST_FP_RET_REG \
: (TARGET_FPU_DOUBLE \ : (TARGET_FPU_DOUBLE \
&& ((MODE) == DFmode || (MODE) == SFmode \ && ((MODE) == DFmode || (MODE) == SFmode \
...@@ -1239,7 +1225,7 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1239,7 +1225,7 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#define FUNCTION_ARG_REGNO_P(REGNO) \ #define FUNCTION_ARG_REGNO_P(REGNO) \
(((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \ (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
&& (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\ && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
|| (TARGET_FPU_ANY \ || (TARGET_FPU_ANY \
&& (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \ && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
&& (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \ && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
+ NPARM_REGS (SFmode)))) + NPARM_REGS (SFmode))))
...@@ -1254,7 +1240,6 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1254,7 +1240,6 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
of arguments scanned so far (including the invisible argument, of arguments scanned so far (including the invisible argument,
if any, which holds the structure-value-address). if any, which holds the structure-value-address).
Thus NARGREGS or more means all following args should go on the stack. */ Thus NARGREGS or more means all following args should go on the stack. */
enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
struct sh_args { struct sh_args {
int arg_count[2]; int arg_count[2];
...@@ -1380,14 +1365,14 @@ struct sh_args { ...@@ -1380,14 +1365,14 @@ struct sh_args {
The SH doesn't care about double alignment, so we only The SH doesn't care about double alignment, so we only
round doubles to even regs when asked to explicitly. */ round doubles to even regs when asked to explicitly. */
#define ROUND_REG(CUM, MODE) \ #define ROUND_REG(CUM, MODE) \
(((TARGET_ALIGN_DOUBLE \ (((TARGET_ALIGN_DOUBLE \
|| ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \ || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
&& (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\ && ((MODE) == DFmode || (MODE) == DCmode) \
&& GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE))) \
? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
+ ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \ ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
+ ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
: (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]) : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
/* Initialize a variable CUM of type CUMULATIVE_ARGS /* Initialize a variable CUM of type CUMULATIVE_ARGS
...@@ -1398,16 +1383,15 @@ struct sh_args { ...@@ -1398,16 +1383,15 @@ struct sh_args {
the same reg for a given argument class. the same reg for a given argument class.
For TARGET_HITACHI, the structure value pointer is passed in memory. */ For TARGET_HITACHI, the structure value pointer is passed in memory. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode) sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\
(N_NAMED_ARGS), VOIDmode)
#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE)) sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
/* Return boolean indicating arg of mode MODE will be passed in a reg. /* Return boolean indicating arg of mode MODE will be passed in a reg.
This macro is only used in this file. */ This macro is only used in this file. */
#define PASS_IN_REG_P(CUM, MODE, TYPE) \ #define PASS_IN_REG_P(CUM, MODE, TYPE) \
(((TYPE) == 0 \ (((TYPE) == 0 \
|| (! TREE_ADDRESSABLE ((TYPE)) \ || (! TREE_ADDRESSABLE ((TYPE)) \
...@@ -1441,7 +1425,7 @@ struct sh_args { ...@@ -1441,7 +1425,7 @@ struct sh_args {
foo (double); a: fr5,fr4 foo (double); a: fr5,fr4
foo (float a, float b); a: fr5 b: fr4 foo (float a, float b); a: fr5 b: fr4
foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency, foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
this should be the other way round... this should be the other way round...
foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */ foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
#define FUNCTION_ARG_SCmode_WART 1 #define FUNCTION_ARG_SCmode_WART 1
...@@ -1524,7 +1508,6 @@ struct sh_args { ...@@ -1524,7 +1508,6 @@ struct sh_args {
We use two .aligns, so as to make sure that both the .long is aligned We use two .aligns, so as to make sure that both the .long is aligned
on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
from the trapa instruction. */ from the trapa instruction. */
#define FUNCTION_PROFILER(STREAM,LABELNO) \ #define FUNCTION_PROFILER(STREAM,LABELNO) \
{ \ { \
if (TARGET_SHMEDIA) \ if (TARGET_SHMEDIA) \
...@@ -1545,22 +1528,20 @@ struct sh_args { ...@@ -1545,22 +1528,20 @@ struct sh_args {
/* Define this macro if the code for function profiling should come /* Define this macro if the code for function profiling should come
before the function prologue. Normally, the profiling code comes before the function prologue. Normally, the profiling code comes
after. */ after. */
#define PROFILE_BEFORE_PROLOGUE #define PROFILE_BEFORE_PROLOGUE
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. The value is tested only in the stack pointer does not matter. The value is tested only in
functions that have frame pointers. functions that have frame pointers.
No definition is equivalent to always zero. */ No definition is equivalent to always zero. */
#define EXIT_IGNORE_STACK 1 #define EXIT_IGNORE_STACK 1
/* /*
On the SH, the trampoline looks like On the SH, the trampoline looks like
2 0002 D202 mov.l l2,r2 2 0002 D202 mov.l l2,r2
1 0000 D301 mov.l l1,r3 1 0000 D301 mov.l l1,r3
3 0004 422B jmp @r2 3 0004 422B jmp @r2
4 0006 0009 nop 4 0006 0009 nop
5 0008 00000000 l1: .long area 5 0008 00000000 l1: .long area
6 000c 00000000 l2: .long function */ 6 000c 00000000 l2: .long function */
...@@ -1577,7 +1558,6 @@ struct sh_args { ...@@ -1577,7 +1558,6 @@ struct sh_args {
address for the frame COUNT steps up from the current frame. address for the frame COUNT steps up from the current frame.
FRAMEADDR is already the frame pointer of the COUNT frame, so we FRAMEADDR is already the frame pointer of the COUNT frame, so we
can ignore COUNT. */ can ignore COUNT. */
#define RETURN_ADDR_RTX(COUNT, FRAME) \ #define RETURN_ADDR_RTX(COUNT, FRAME) \
(((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX) (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX)
...@@ -1594,11 +1574,11 @@ struct sh_args { ...@@ -1594,11 +1574,11 @@ struct sh_args {
#define HAVE_PRE_DECREMENT TARGET_SH1 #define HAVE_PRE_DECREMENT TARGET_SH1
#define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \ #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
? 0 : TARGET_SH1) ? 0 : TARGET_SH1)
#define USE_LOAD_PRE_DECREMENT(mode) 0 #define USE_LOAD_PRE_DECREMENT(mode) 0
#define USE_STORE_POST_INCREMENT(mode) 0 #define USE_STORE_POST_INCREMENT(mode) 0
#define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \ #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
? 0 : TARGET_SH1) ? 0 : TARGET_SH1)
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \ #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
(move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \ (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
...@@ -1618,7 +1598,6 @@ struct sh_args { ...@@ -1618,7 +1598,6 @@ struct sh_args {
Since they use reg_renumber, they are safe only once reg_renumber Since they use reg_renumber, they are safe only once reg_renumber
has been allocated, which happens in reginfo.c during register has been allocated, which happens in reginfo.c during register
allocation. */ allocation. */
#define REGNO_OK_FOR_BASE_P(REGNO) \ #define REGNO_OK_FOR_BASE_P(REGNO) \
(GENERAL_OR_AP_REGISTER_P (REGNO) \ (GENERAL_OR_AP_REGISTER_P (REGNO) \
|| GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
...@@ -1630,11 +1609,9 @@ struct sh_args { ...@@ -1630,11 +1609,9 @@ struct sh_args {
/* Maximum number of registers that can appear in a valid memory /* Maximum number of registers that can appear in a valid memory
address. */ address. */
#define MAX_REGS_PER_ADDRESS 2 #define MAX_REGS_PER_ADDRESS 2
/* Recognize any constant value that is a valid address. */ /* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
...@@ -1661,7 +1638,7 @@ struct sh_args { ...@@ -1661,7 +1638,7 @@ struct sh_args {
/* Macros for extra constraints. */ /* Macros for extra constraints. */
#define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \ #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
((GET_CODE ((OP)) == LABEL_REF) \ ((GET_CODE ((OP)) == LABEL_REF) \
|| (GET_CODE ((OP)) == CONST \ || (GET_CODE ((OP)) == CONST \
&& GET_CODE (XEXP ((OP), 0)) == PLUS \ && GET_CODE (XEXP ((OP), 0)) == PLUS \
...@@ -1670,7 +1647,7 @@ struct sh_args { ...@@ -1670,7 +1647,7 @@ struct sh_args {
#define IS_NON_EXPLICIT_CONSTANT_P(OP) \ #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
(CONSTANT_P (OP) \ (CONSTANT_P (OP) \
&& !CONST_INT_P (OP) \ && !CONST_INT_P (OP) \
&& GET_CODE (OP) != CONST_DOUBLE \ && GET_CODE (OP) != CONST_DOUBLE \
&& (!flag_pic \ && (!flag_pic \
|| (LEGITIMATE_PIC_OPERAND_P (OP) \ || (LEGITIMATE_PIC_OPERAND_P (OP) \
...@@ -1699,7 +1676,7 @@ struct sh_args { ...@@ -1699,7 +1676,7 @@ struct sh_args {
(GET_CODE (OP) == CONST \ (GET_CODE (OP) == CONST \
&& (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
|| (GET_CODE (XEXP ((OP), 0)) == PLUS \ || (GET_CODE (XEXP ((OP), 0)) == PLUS \
&& UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
&& CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))) && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
#define PIC_ADDR_P(OP) \ #define PIC_ADDR_P(OP) \
...@@ -1766,7 +1743,6 @@ struct sh_args { ...@@ -1766,7 +1743,6 @@ struct sh_args {
/* A C compound statement that attempts to replace X, which is an address /* A C compound statement that attempts to replace X, which is an address
that needs reloading, with a valid memory address for an operand of that needs reloading, with a valid memory address for an operand of
mode MODE. WIN is a C statement label elsewhere in the code. */ mode MODE. WIN is a C statement label elsewhere in the code. */
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
do { \ do { \
if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
...@@ -1796,7 +1772,8 @@ struct sh_args { ...@@ -1796,7 +1772,8 @@ struct sh_args {
/* Since the SH2e has only `float' support, it is desirable to make all /* Since the SH2e has only `float' support, it is desirable to make all
floating point types equivalent to `float'. */ floating point types equivalent to `float'. */
#define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64) #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE)\
? 32 : 64)
/* 'char' is signed by default. */ /* 'char' is signed by default. */
#define DEFAULT_SIGNED_CHAR 1 #define DEFAULT_SIGNED_CHAR 1
...@@ -1831,9 +1808,9 @@ struct sh_args { ...@@ -1831,9 +1808,9 @@ struct sh_args {
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly be the code that says which one of the two operations is implicitly
done, UNKNOWN if none. */ done, UNKNOWN if none.
/* For SHmedia, we can truncate to QImode easier using zero extension. */ For SHmedia, we can truncate to QImode easier using zero extension.
/* FP registers can load SImode values, but don't implicitly sign-extend FP registers can load SImode values, but don't implicitly sign-extend
them to DImode. */ them to DImode. */
#define LOAD_EXTEND_OP(MODE) \ #define LOAD_EXTEND_OP(MODE) \
(((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \ (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
...@@ -1901,14 +1878,14 @@ struct sh_args { ...@@ -1901,14 +1878,14 @@ struct sh_args {
in particular. */ in particular. */
#define INSN_SETS_ARE_DELAYED(X) \ #define INSN_SETS_ARE_DELAYED(X) \
((NONJUMP_INSN_P (X) \ ((NONJUMP_INSN_P (X) \
&& GET_CODE (PATTERN (X)) != SEQUENCE \ && GET_CODE (PATTERN (X)) != SEQUENCE \
&& GET_CODE (PATTERN (X)) != USE \ && GET_CODE (PATTERN (X)) != USE \
&& GET_CODE (PATTERN (X)) != CLOBBER \ && GET_CODE (PATTERN (X)) != CLOBBER \
&& get_attr_is_sfunc (X))) && get_attr_is_sfunc (X)))
#define INSN_REFERENCES_ARE_DELAYED(X) \ #define INSN_REFERENCES_ARE_DELAYED(X) \
((NONJUMP_INSN_P (X) \ ((NONJUMP_INSN_P (X) \
&& GET_CODE (PATTERN (X)) != SEQUENCE \ && GET_CODE (PATTERN (X)) != SEQUENCE \
&& GET_CODE (PATTERN (X)) != USE \ && GET_CODE (PATTERN (X)) != USE \
&& GET_CODE (PATTERN (X)) != CLOBBER \ && GET_CODE (PATTERN (X)) != CLOBBER \
...@@ -1936,7 +1913,6 @@ struct sh_args { ...@@ -1936,7 +1913,6 @@ struct sh_args {
/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
uses this information. Hence, the general register <-> floating point uses this information. Hence, the general register <-> floating point
register information here is not used for SFmode. */ register information here is not used for SFmode. */
#define REGCLASS_HAS_GENERAL_REG(CLASS) \ #define REGCLASS_HAS_GENERAL_REG(CLASS) \
((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \ ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
|| (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
...@@ -1966,9 +1942,10 @@ struct sh_args { ...@@ -1966,9 +1942,10 @@ struct sh_args {
#define SET_ASM_OP "\t.set\t" #define SET_ASM_OP "\t.set\t"
/* How to change between sections. */ /* How to change between sections. */
#define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 \
#define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text") ? "\t.section\t.text..SHmedia32,\"ax\"" \
#define DATA_SECTION_ASM_OP "\t.data" : "\t.text")
#define DATA_SECTION_ASM_OP "\t.data"
#if defined CRT_BEGIN || defined CRT_END #if defined CRT_BEGIN || defined CRT_END
/* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
...@@ -2060,7 +2037,7 @@ struct sh_args { ...@@ -2060,7 +2037,7 @@ struct sh_args {
(unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \ FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \ ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
: ((int) (REGNO) >= FIRST_FP_REG \ : ((int) (REGNO) >= FIRST_FP_REG \
&& ((int) (REGNO) \ && ((int) (REGNO) \
<= (FIRST_FP_REG + \ <= (FIRST_FP_REG + \
((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \ ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
...@@ -2110,11 +2087,10 @@ struct sh_args { ...@@ -2110,11 +2087,10 @@ struct sh_args {
/* Globalizing directive for a label. */ /* Globalizing directive for a label. */
#define GLOBAL_ASM_OP "\t.global\t" #define GLOBAL_ASM_OP "\t.global\t"
/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
/* Output a relative address table. */ /* Output a relative address table. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
switch (GET_MODE (BODY)) \ switch (GET_MODE (BODY)) \
{ \ { \
case SImode: \ case SImode: \
...@@ -2149,7 +2125,6 @@ struct sh_args { ...@@ -2149,7 +2125,6 @@ struct sh_args {
} }
/* Output an absolute table element. */ /* Output an absolute table element. */
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
if (! optimize || TARGET_BIGTABLE) \ if (! optimize || TARGET_BIGTABLE) \
asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
...@@ -2167,7 +2142,6 @@ struct sh_args { ...@@ -2167,7 +2142,6 @@ struct sh_args {
The contents of this vector are what will be used to convert the insn The contents of this vector are what will be used to convert the insn
template into assembler code, so you can change the assembler output template into assembler code, so you can change the assembler output
by changing the contents of the vector. */ by changing the contents of the vector. */
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
...@@ -2177,7 +2151,6 @@ extern rtx sh_compare_op1; ...@@ -2177,7 +2151,6 @@ extern rtx sh_compare_op1;
/* Which processor to schedule for. The elements of the enumeration must /* Which processor to schedule for. The elements of the enumeration must
match exactly the cpu attribute in the sh.md file. */ match exactly the cpu attribute in the sh.md file. */
enum processor_type { enum processor_type {
PROCESSOR_SH1, PROCESSOR_SH1,
PROCESSOR_SH2, PROCESSOR_SH2,
...@@ -2216,14 +2189,12 @@ extern tree sh_deferred_function_attributes; ...@@ -2216,14 +2189,12 @@ extern tree sh_deferred_function_attributes;
extern tree *sh_deferred_function_attributes_tail; extern tree *sh_deferred_function_attributes_tail;
/* Set when processing a function with interrupt attribute. */ /* Set when processing a function with interrupt attribute. */
extern int current_function_interrupt; extern int current_function_interrupt;
/* Instructions with unfilled delay slots take up an /* Instructions with unfilled delay slots take up an
extra two bytes for the nop in the delay slot. extra two bytes for the nop in the delay slot.
sh-dsp parallel processing insns are four bytes long. */ sh-dsp parallel processing insns are four bytes long. */
#define ADJUST_INSN_LENGTH(X, LENGTH) \ #define ADJUST_INSN_LENGTH(X, LENGTH) \
(LENGTH) += sh_insn_length_adjustment (X); (LENGTH) += sh_insn_length_adjustment (X);
...@@ -2266,8 +2237,8 @@ extern int current_function_interrupt; ...@@ -2266,8 +2237,8 @@ extern int current_function_interrupt;
#define MODE_EXIT(ENTITY) \ #define MODE_EXIT(ENTITY) \
(sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY)) (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
#define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \ #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
&& (REGNO) == FPSCR_REG) && (REGNO) == FPSCR_REG)
#define MODE_NEEDED(ENTITY, INSN) \ #define MODE_NEEDED(ENTITY, INSN) \
(recog_memoized (INSN) >= 0 \ (recog_memoized (INSN) >= 0 \
...@@ -2277,8 +2248,8 @@ extern int current_function_interrupt; ...@@ -2277,8 +2248,8 @@ extern int current_function_interrupt;
#define MODE_AFTER(ENTITY, MODE, INSN) \ #define MODE_AFTER(ENTITY, MODE, INSN) \
(TARGET_HITACHI \ (TARGET_HITACHI \
&& recog_memoized (INSN) >= 0 \ && recog_memoized (INSN) >= 0 \
&& get_attr_fp_set (INSN) != FP_SET_NONE \ && get_attr_fp_set (INSN) != FP_SET_NONE \
? (int) get_attr_fp_set (INSN) \ ? (int) get_attr_fp_set (INSN) \
: (MODE)) : (MODE))
#define MODE_PRIORITY_TO_MODE(ENTITY, N) \ #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
......
gcc/config/sh/sh.md
...@@ -195,7 +195,7 @@ ...@@ -195,7 +195,7 @@
;; Indicate if the default fpu mode is single precision. ;; Indicate if the default fpu mode is single precision.
(define_attr "fpu_single" "yes,no" (define_attr "fpu_single" "yes,no"
(const (if_then_else (symbol_ref "TARGET_FPU_SINGLE") (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
(const_string "yes") (const_string "no")))) (const_string "yes") (const_string "no"))))
(define_attr "fmovd" "yes,no" (define_attr "fmovd" "yes,no"
(const (if_then_else (symbol_ref "TARGET_FMOVD") (const (if_then_else (symbol_ref "TARGET_FMOVD")
...@@ -282,7 +282,16 @@ ...@@ -282,7 +282,16 @@
;; nil no-op move, will be deleted. ;; nil no-op move, will be deleted.
(define_attr "type" (define_attr "type"
"mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other" "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,
dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,
fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,
jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,
d2mpy_media,atrans_media,ustore_media,nil,other"
(const_string "other")) (const_string "other"))
;; We define a new attribute namely "insn_class".We use ;; We define a new attribute namely "insn_class".We use
...@@ -294,23 +303,25 @@ ...@@ -294,23 +303,25 @@
;; ;;
;; ls_group SH4 "ls" group instructions. ;; ls_group SH4 "ls" group instructions.
;; ;;
(define_attr "insn_class" (define_attr "insn_class"
"mt_group,ex_group,ls_group,br_group,fe_group,co_group,none" "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
(cond [(eq_attr "type" "move,mt_group") (const_string "mt_group") (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
(eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group") (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
(eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,store,fstore,gp_fpul,fpul_gp") (const_string "ls_group") (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
(eq_attr "type" "cbranch,jump") (const_string "br_group") (eq_attr "type" "cbranch,jump") (const_string "br_group")
(eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv") (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
(const_string "fe_group") (const_string "fe_group")
(eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,gp_mac,mac_mem,mem_mac") (const_string "co_group")] (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
gp_mac,mac_mem,mem_mac") (const_string "co_group")]
(const_string "none"))) (const_string "none")))
;; nil are zero instructions, and arith3 / arith3b are multiple instructions, ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
;; so these do not belong in an insn group, although they are modeled ;; so these do not belong in an insn group, although they are modeled
;; with their own define_insn_reservations. ;; with their own define_insn_reservations.
;; Indicate what precision must be selected in fpscr for this insn, if any. ;; Indicate what precision must be selected in fpscr for this insn, if any.
(define_attr "fp_mode" "single,double,none" (const_string "none")) (define_attr "fp_mode" "single,double,none" (const_string "none"))
;; Indicate if the fpu mode is set by this instruction ;; Indicate if the fpu mode is set by this instruction
...@@ -355,7 +366,7 @@ ...@@ -355,7 +366,7 @@
(const_string "no") (const_string "no")
(leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508)) (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
(const_string "yes") (const_string "yes")
] (const_string "no"))) ] (const_string "no")))
(define_attr "med_branch_p" "no,yes" (define_attr "med_branch_p" "no,yes"
(cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990)) (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
...@@ -405,14 +416,14 @@ ...@@ -405,14 +416,14 @@
(const_string "yes") (const_string "yes")
] (const_string "no"))) ] (const_string "no")))
; An unconditional jump in the range -4092..4098 can be 2 bytes long. ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
; For wider ranges, we need a combination of a code and a data part. ;; For wider ranges, we need a combination of a code and a data part.
; If we can get a scratch register for a long range jump, the code ;; If we can get a scratch register for a long range jump, the code
; part can be 4 bytes long; otherwise, it must be 8 bytes long. ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
; If the jump is in the range -32764..32770, the data part can be 2 bytes ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
; long; otherwise, it must be 6 bytes long. ;; long; otherwise, it must be 6 bytes long.
; All other instructions are two bytes long by default. ;; All other instructions are two bytes long by default.
;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)), ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
;; but getattrtab doesn't understand this. ;; but getattrtab doesn't understand this.
...@@ -434,14 +445,16 @@ ...@@ -434,14 +445,16 @@
(cond [(eq_attr "med_branch_p" "yes") (cond [(eq_attr "med_branch_p" "yes")
(const_int 2) (const_int 2)
(and (match_test "prev_nonnote_insn (insn)") (and (match_test "prev_nonnote_insn (insn)")
(and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))") (symbol_ref "INSN")) (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
(eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))") (symbol_ref "code_for_indirect_jump_scratch")))) (symbol_ref "INSN"))
(cond [(eq_attr "braf_branch_p" "yes") (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
(const_int 6) (symbol_ref "code_for_indirect_jump_scratch"))))
(not (match_test "flag_pic")) (cond [(eq_attr "braf_branch_p" "yes")
(const_int 10) (const_int 6)
(match_test "TARGET_SH2") (not (match_test "flag_pic"))
(const_int 10)] (const_int 18)) (const_int 10)
(match_test "TARGET_SH2")
(const_int 10)] (const_int 18))
(eq_attr "braf_branch_p" "yes") (eq_attr "braf_branch_p" "yes")
(const_int 10) (const_int 10)
;; ??? using pc is not computed transitively. ;; ??? using pc is not computed transitively.
...@@ -596,7 +609,6 @@ ...@@ -596,7 +609,6 @@
;; Usual TST #imm, R0 patterns for SI, HI and QI ;; Usual TST #imm, R0 patterns for SI, HI and QI
;; This is usually used for bit patterns other than contiguous bits ;; This is usually used for bit patterns other than contiguous bits
;; and single bits. ;; and single bits.
(define_insn "tstsi_t" (define_insn "tstsi_t"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(eq:SI (and:SI (match_operand:SI 0 "logical_operand" "%z,r") (eq:SI (and:SI (match_operand:SI 0 "logical_operand" "%z,r")
...@@ -632,7 +644,6 @@ ...@@ -632,7 +644,6 @@
;; Test low QI subreg against zero. ;; Test low QI subreg against zero.
;; This avoids unnecessary zero extension before the test. ;; This avoids unnecessary zero extension before the test.
(define_insn "*tstqi_t_zero" (define_insn "*tstqi_t_zero"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(eq:SI (match_operand:QI 0 "logical_operand" "z") (const_int 0)))] (eq:SI (match_operand:QI 0 "logical_operand" "z") (const_int 0)))]
...@@ -667,7 +678,6 @@ ...@@ -667,7 +678,6 @@
[(set_attr "type" "mt_group")]) [(set_attr "type" "mt_group")])
;; Extract LSB, negate and store in T bit. ;; Extract LSB, negate and store in T bit.
(define_insn "tstsi_t_and_not" (define_insn "tstsi_t_and_not"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(and:SI (not:SI (match_operand:SI 0 "logical_operand" "z")) (and:SI (not:SI (match_operand:SI 0 "logical_operand" "z"))
...@@ -677,13 +687,12 @@ ...@@ -677,13 +687,12 @@
[(set_attr "type" "mt_group")]) [(set_attr "type" "mt_group")])
;; Extract contiguous bits and compare them against zero. ;; Extract contiguous bits and compare them against zero.
(define_insn "tstsi_t_zero_extract_eq" (define_insn "tstsi_t_zero_extract_eq"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(eq:SI (zero_extract:SI (match_operand 0 "logical_operand" "z") (eq:SI (zero_extract:SI (match_operand 0 "logical_operand" "z")
(match_operand:SI 1 "const_int_operand") (match_operand:SI 1 "const_int_operand")
(match_operand:SI 2 "const_int_operand")) (match_operand:SI 2 "const_int_operand"))
(const_int 0)))] (const_int 0)))]
"TARGET_SH1 "TARGET_SH1
&& CONST_OK_FOR_K08 (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]))" && CONST_OK_FOR_K08 (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]))"
{ {
...@@ -693,15 +702,15 @@ ...@@ -693,15 +702,15 @@
[(set_attr "type" "mt_group")]) [(set_attr "type" "mt_group")])
;; This split is required when testing bits in a QI subreg. ;; This split is required when testing bits in a QI subreg.
(define_split (define_split
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(eq:SI (if_then_else:SI (zero_extract:SI (eq:SI
(match_operand 0 "logical_operand" "") (if_then_else:SI
(match_operand 1 "const_int_operand") (zero_extract:SI (match_operand 0 "logical_operand")
(match_operand 2 "const_int_operand")) (match_operand 1 "const_int_operand")
(match_operand 3 "const_int_operand") (match_operand 2 "const_int_operand"))
(const_int 0)) (match_operand 3 "const_int_operand")
(const_int 0))
(const_int 0)))] (const_int 0)))]
"TARGET_SH1 "TARGET_SH1
&& ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3]) && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
...@@ -715,11 +724,10 @@ ...@@ -715,11 +724,10 @@
;; Extract single bit, negate and store it in the T bit. ;; Extract single bit, negate and store it in the T bit.
;; Not used for SH4A. ;; Not used for SH4A.
(define_insn "tstsi_t_zero_extract_xor" (define_insn "tstsi_t_zero_extract_xor"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(zero_extract:SI (xor:SI (match_operand:SI 0 "logical_operand" "z") (zero_extract:SI (xor:SI (match_operand:SI 0 "logical_operand" "z")
(match_operand:SI 3 "const_int_operand")) (match_operand:SI 3 "const_int_operand"))
(match_operand:SI 1 "const_int_operand") (match_operand:SI 1 "const_int_operand")
(match_operand:SI 2 "const_int_operand")))] (match_operand:SI 2 "const_int_operand")))]
"TARGET_SH1 "TARGET_SH1
...@@ -730,7 +738,6 @@ ...@@ -730,7 +738,6 @@
;; Extract single bit, negate and store it in the T bit. ;; Extract single bit, negate and store it in the T bit.
;; Used for SH4A little endian. ;; Used for SH4A little endian.
(define_insn "tstsi_t_zero_extract_subreg_xor_little" (define_insn "tstsi_t_zero_extract_subreg_xor_little"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(zero_extract:SI (zero_extract:SI
...@@ -750,7 +757,6 @@ ...@@ -750,7 +757,6 @@
;; Extract single bit, negate and store it in the T bit. ;; Extract single bit, negate and store it in the T bit.
;; Used for SH4A big endian. ;; Used for SH4A big endian.
(define_insn "tstsi_t_zero_extract_subreg_xor_big" (define_insn "tstsi_t_zero_extract_subreg_xor_big"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(zero_extract:SI (zero_extract:SI
...@@ -890,7 +896,6 @@ ...@@ -890,7 +896,6 @@
(const_int 0))) (const_int 0)))
(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]) (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
;; SImode compare and branch ;; SImode compare and branch
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
...@@ -918,7 +923,6 @@ ...@@ -918,7 +923,6 @@
;; don't have actual comparison insns. These patterns are used in cases ;; don't have actual comparison insns. These patterns are used in cases
;; which appear after the initial cbranchsi expansion, which also does ;; which appear after the initial cbranchsi expansion, which also does
;; some condition inversion. ;; some condition inversion.
(define_split (define_split
[(set (pc) [(set (pc)
(if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "") (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
...@@ -1093,13 +1097,11 @@ ...@@ -1093,13 +1097,11 @@
"TARGET_SH1" "TARGET_SH1"
"cmp/hi %1,%0" "cmp/hi %1,%0"
[(set_attr "type" "mt_group")]) [(set_attr "type" "mt_group")])
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
;; DImode compare and branch ;; DImode compare and branch
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism. ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
;; Therefore, we aim to have a set of three branches that go straight to the ;; Therefore, we aim to have a set of three branches that go straight to the
;; destination, i.e. only one of them is taken at any one time. ;; destination, i.e. only one of them is taken at any one time.
...@@ -1124,13 +1126,11 @@ ...@@ -1124,13 +1126,11 @@
operands[2], operands[3])); operands[2], operands[3]));
DONE; DONE;
} }
else if (!TARGET_CBRANCHDI4) else if (!TARGET_CBRANCHDI4)
{ {
sh_emit_compare_and_branch (operands, DImode); sh_emit_compare_and_branch (operands, DImode);
DONE; DONE;
} }
else else
{ {
if (expand_cbranchdi4 (operands, LAST_AND_UNUSED_RTX_CODE)) if (expand_cbranchdi4 (operands, LAST_AND_UNUSED_RTX_CODE))
...@@ -1139,8 +1139,8 @@ ...@@ -1139,8 +1139,8 @@
comparison = prepare_cbranch_operands (operands, DImode, comparison = prepare_cbranch_operands (operands, DImode,
LAST_AND_UNUSED_RTX_CODE); LAST_AND_UNUSED_RTX_CODE);
if (comparison != GET_CODE (operands[0])) if (comparison != GET_CODE (operands[0]))
operands[0] operands[0]
= gen_rtx_fmt_ee (comparison, VOIDmode, operands[1], operands[2]); = gen_rtx_fmt_ee (comparison, VOIDmode, operands[1], operands[2]);
operands[4] = gen_rtx_SCRATCH (SImode); operands[4] = gen_rtx_SCRATCH (SImode);
} }
}) })
...@@ -1440,7 +1440,7 @@ ...@@ -1440,7 +1440,7 @@
operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]), operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
GET_CODE (operands[1]), GET_CODE (operands[1]),
XEXP (operands[1], 0), XEXP (operands[1], 0),
XEXP (operands[1], 1)); XEXP (operands[1], 1));
if (!operands[1]) if (!operands[1])
FAIL; FAIL;
} }
...@@ -1681,7 +1681,7 @@ ...@@ -1681,7 +1681,7 @@
operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]), operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
GET_CODE (operands[1]), GET_CODE (operands[1]),
XEXP (operands[1], 0), XEXP (operands[1], 0),
XEXP (operands[1], 1)); XEXP (operands[1], 1));
if (!operands[1]) if (!operands[1])
FAIL; FAIL;
} }
...@@ -1714,7 +1714,7 @@ ...@@ -1714,7 +1714,7 @@
if (TARGET_SH1) if (TARGET_SH1)
{ {
if (!can_create_pseudo_p () && ! arith_reg_operand (operands[2], DImode)) if (!can_create_pseudo_p () && ! arith_reg_operand (operands[2], DImode))
FAIL; FAIL;
operands[2] = force_reg (DImode, operands[2]); operands[2] = force_reg (DImode, operands[2]);
emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2])); emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
DONE; DONE;
...@@ -2078,11 +2078,18 @@ ...@@ -2078,11 +2078,18 @@
[(set (match_dup 0) (zero_extend:SI (match_dup 1))) [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
(set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))] (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
"") "")
;; Convert `constant - reg' to `neg rX; add rX, #const' since this
;; will sometimes save one instruction. Otherwise we might get
;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
;; are the same.
;; Convert
;; constant - reg
;; to
;; neg reg
;; add reg, #const
;; since this will sometimes save one instruction.
;; Otherwise we might get a sequence like
;; mov #const, rY
;; sub rY, rX
;; mov rX, rY
;; if the source and dest regs are the same.
(define_expand "subsi3" (define_expand "subsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "") [(set (match_operand:SI 0 "arith_reg_operand" "")
(minus:SI (match_operand:SI 1 "arith_operand" "") (minus:SI (match_operand:SI 1 "arith_operand" "")
...@@ -2140,7 +2147,6 @@ ...@@ -2140,7 +2147,6 @@
;; there is nothing to prevent reload from using r0 to reload the address. ;; there is nothing to prevent reload from using r0 to reload the address.
;; This reload would clobber the value in r0 we are trying to store. ;; This reload would clobber the value in r0 we are trying to store.
;; If we let reload allocate r0, then this problem can never happen. ;; If we let reload allocate r0, then this problem can never happen.
(define_insn "udivsi3_i1" (define_insn "udivsi3_i1"
[(set (match_operand:SI 0 "register_operand" "=z") [(set (match_operand:SI 0 "register_operand" "=z")
(udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
...@@ -2678,7 +2684,6 @@ ...@@ -2678,7 +2684,6 @@
;; These are unspecs because we could generate an indexed addressing mode ;; These are unspecs because we could generate an indexed addressing mode
;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would ;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would
;; confuse reload. See PR27117. ;; confuse reload. See PR27117.
(define_insn "divsi_inv_qitable" (define_insn "divsi_inv_qitable"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r") (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r")
...@@ -3199,7 +3204,6 @@ label: ...@@ -3199,7 +3204,6 @@ label:
;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
;; a call to a routine which clobbers known registers. ;; a call to a routine which clobbers known registers.
(define_insn "" (define_insn ""
[(set (match_operand:SI 1 "register_operand" "=z") [(set (match_operand:SI 1 "register_operand" "=z")
(mult:SI (reg:SI R4_REG) (reg:SI R5_REG))) (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
...@@ -3525,7 +3529,6 @@ label: ...@@ -3525,7 +3529,6 @@ label:
emit_insn (gen_adddi3 (operands[0], operands[4], operands[0])); emit_insn (gen_adddi3 (operands[0], operands[4], operands[0]));
DONE; DONE;
}) })
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
;; Logical operations ;; Logical operations
...@@ -5343,9 +5346,9 @@ label: ...@@ -5343,9 +5346,9 @@ label:
(const_string "14"))) (const_string "14")))
(set_attr "type" "arith")]) (set_attr "type" "arith")])
;; These patterns are found in expansions of DImode shifts by 16, and ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
;; allow the xtrct instruction to be generated from C source. ;; shifts by 16, and allow the xtrct instruction to be generated from C
;; source.
(define_insn "xtrct_left" (define_insn "xtrct_left"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r") (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
...@@ -5552,7 +5555,6 @@ label: ...@@ -5552,7 +5555,6 @@ label:
;; Actually the instruction scheduling should decide whether to use a ;; Actually the instruction scheduling should decide whether to use a
;; zero-offset branch or not for any generic case involving a single ;; zero-offset branch or not for any generic case involving a single
;; instruction on SH4 202. ;; instruction on SH4 202.
(define_insn_and_split "negsi_cond" (define_insn_and_split "negsi_cond"
[(set (match_operand:SI 0 "arith_reg_dest" "=r,r") [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
(if_then_else (if_then_else
...@@ -5727,7 +5729,6 @@ label: ...@@ -5727,7 +5729,6 @@ label:
(const_int 65280)) (const_int 65280))
(and:SI (ashiftrt:SI (match_dup 1) (const_int 8)) (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
(const_int 255)))))]) (const_int 255)))))])
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
;; Zero extension instructions ;; Zero extension instructions
...@@ -5805,9 +5806,9 @@ label: ...@@ -5805,9 +5806,9 @@ label:
{ {
/* Sometimes combine fails to combine a T bit or negated T bit store to a /* Sometimes combine fails to combine a T bit or negated T bit store to a
reg with a following zero extension. In the split pass after combine, reg with a following zero extension. In the split pass after combine,
try to figure the extended reg was set. If it originated from the T try to figure out how the extended reg was set. If it originated from
bit we can replace the zero extension with a reg move, which will be the T bit we can replace the zero extension with a reg move, which will
eliminated. Notice that this also helps the *cbranch_t splitter when be eliminated. Notice that this also helps the *cbranch_t splitter when
it tries to post-combine tests and conditional branches, as it does not it tries to post-combine tests and conditional branches, as it does not
check for zero extensions. */ check for zero extensions. */
operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn); operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
...@@ -6155,7 +6156,8 @@ label: ...@@ -6155,7 +6156,8 @@ label:
fmov.ls %1, %0 fmov.ls %1, %0
fmov.sl %T1, %0 fmov.sl %T1, %0
fmov.s %T1, %0" fmov.s %T1, %0"
[(set_attr "type" "arith_media,store_media,fstore_media,fload_media,fpconv_media,fmove_media") [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,
fpconv_media,fmove_media")
(set (attr "highpart") (set (attr "highpart")
(cond [(match_test "sh_contains_memref_p (insn)") (cond [(match_test "sh_contains_memref_p (insn)")
(const_string "user")] (const_string "user")]
...@@ -6197,6 +6199,7 @@ label: ...@@ -6197,6 +6199,7 @@ label:
(cond [(match_test "sh_contains_memref_p (insn)") (cond [(match_test "sh_contains_memref_p (insn)")
(const_string "user")] (const_string "user")]
(const_string "extend")))]) (const_string "extend")))])
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
;; Move instructions ;; Move instructions
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
...@@ -6204,7 +6207,6 @@ label: ...@@ -6204,7 +6207,6 @@ label:
;; define push and pop so it is easy for sh.c ;; define push and pop so it is easy for sh.c
;; We can't use push and pop on SHcompact because the stack must always ;; We can't use push and pop on SHcompact because the stack must always
;; be 8-byte aligned. ;; be 8-byte aligned.
(define_expand "push" (define_expand "push"
[(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
(match_operand:SI 0 "register_operand" "r,l,x"))] (match_operand:SI 0 "register_operand" "r,l,x"))]
...@@ -6298,7 +6300,6 @@ label: ...@@ -6298,7 +6300,6 @@ label:
;; When DImode operations that use the T reg as carry/borrow are split into ;; When DImode operations that use the T reg as carry/borrow are split into
;; individual SImode operations, the T reg is usually cleared before the ;; individual SImode operations, the T reg is usually cleared before the
;; first SImode insn. ;; first SImode insn.
(define_insn "clrt" (define_insn "clrt"
[(set (reg:SI T_REG) (const_int 0))] [(set (reg:SI T_REG) (const_int 0))]
"TARGET_SH1" "TARGET_SH1"
...@@ -6460,7 +6461,8 @@ label: ...@@ -6460,7 +6461,8 @@ label:
lds.l %1,%0 lds.l %1,%0
lds.l %1,%0 lds.l %1,%0
fake %1,%0" fake %1,%0"
[(set_attr "type" "pcload_si,move,movi8,load_si,mac_gp,prget,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si") [(set_attr "type" "pcload_si,move,movi8,load_si,mac_gp,prget,store,mac_mem,
pstore,gp_mac,prset,mem_mac,pload,pcload_si")
(set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*")]) (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
;; t/r must come after r/r, lest reload will try to reload stuff like ;; t/r must come after r/r, lest reload will try to reload stuff like
...@@ -6502,7 +6504,9 @@ label: ...@@ -6502,7 +6504,9 @@ label:
flds %1,fpul flds %1,fpul
fmov %1,%0 fmov %1,%0
! move optimized away" ! move optimized away"
[(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil") [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
(set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*") (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
(set_attr_alternative "length" (set_attr_alternative "length"
[(const_int 2) [(const_int 2)
...@@ -6535,7 +6539,8 @@ label: ...@@ -6535,7 +6539,8 @@ label:
(const_int 0)])]) (const_int 0)])])
(define_insn "movsi_i_lowpart" (define_insn "movsi_i_lowpart"
[(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r")) [(set (strict_low_part
(match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
(match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,r,i"))] (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,r,i"))]
"TARGET_SH1 "TARGET_SH1
&& (register_operand (operands[0], SImode) && (register_operand (operands[0], SImode)
...@@ -6589,7 +6594,9 @@ label: ...@@ -6589,7 +6594,9 @@ label:
ptabs %1, %0 ptabs %1, %0
gettr %1, %0 gettr %1, %0
pt %1, %0" pt %1, %0"
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,fpconv_media,fmove_media,ptabs_media,gettr_media,pt_media") [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
fload_media,fstore_media,fload_media,fpconv_media,
fmove_media,ptabs_media,gettr_media,pt_media")
(set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12") (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")
(set (attr "highpart") (set (attr "highpart")
(cond [(match_test "sh_contains_memref_p (insn)") (cond [(match_test "sh_contains_memref_p (insn)")
...@@ -6614,7 +6621,8 @@ label: ...@@ -6614,7 +6621,8 @@ label:
ptabs %1, %0 ptabs %1, %0
gettr %1, %0 gettr %1, %0
pt %1, %0" pt %1, %0"
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media") [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
ptabs_media,gettr_media,pt_media")
(set_attr "length" "4,4,8,4,4,4,4,12") (set_attr "length" "4,4,8,4,4,4,4,12")
(set (attr "highpart") (set (attr "highpart")
(cond [(match_test "sh_contains_memref_p (insn)") (cond [(match_test "sh_contains_memref_p (insn)")
...@@ -7015,7 +7023,6 @@ label: ...@@ -7015,7 +7023,6 @@ label:
;; If the output is a register and the input is memory or a register, we have ;; If the output is a register and the input is memory or a register, we have
;; to be careful and see which word needs to be loaded first. ;; to be careful and see which word needs to be loaded first.
(define_split (define_split
[(set (match_operand:DI 0 "general_movdst_operand" "") [(set (match_operand:DI 0 "general_movdst_operand" "")
(match_operand:DI 1 "general_movsrc_operand" ""))] (match_operand:DI 1 "general_movsrc_operand" ""))]
...@@ -7092,7 +7099,9 @@ label: ...@@ -7092,7 +7099,9 @@ label:
ptabs %1, %0 ptabs %1, %0
gettr %1, %0 gettr %1, %0
pt %1, %0" pt %1, %0"
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,dfpconv_media,fmove_media,ptabs_media,gettr_media,pt_media") [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
fload_media,fstore_media,fload_media,dfpconv_media,
fmove_media,ptabs_media,gettr_media,pt_media")
(set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")]) (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
(define_insn "*movdi_media_nofpu" (define_insn "*movdi_media_nofpu"
...@@ -7110,7 +7119,8 @@ label: ...@@ -7110,7 +7119,8 @@ label:
ptabs %1, %0 ptabs %1, %0
gettr %1, %0 gettr %1, %0
pt %1, %0" pt %1, %0"
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media") [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
ptabs_media,gettr_media,pt_media")
(set_attr "length" "4,4,16,4,4,4,4,*")]) (set_attr "length" "4,4,16,4,4,4,4,*")])
(define_insn "*movdi_media_I16" (define_insn "*movdi_media_I16"
...@@ -7369,7 +7379,8 @@ label: ...@@ -7369,7 +7379,8 @@ label:
fst%M0.d %m0, %1 fst%M0.d %m0, %1
ld%M1.q %m1, %0 ld%M1.q %m1, %0
st%M0.q %m0, %N1" st%M0.q %m0, %N1"
[(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")]) [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,
fload_media,fstore_media,load_media,store_media")])
(define_insn "movdf_media_nofpu" (define_insn "movdf_media_nofpu"
[(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m") [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
...@@ -7411,8 +7422,7 @@ label: ...@@ -7411,8 +7422,7 @@ label:
operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0])); operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
}) })
;; ??? This should be a define expand. ;; FIXME: This should be a define_insn_and_split.
(define_insn "movdf_k" (define_insn "movdf_k"
[(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m") [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
(match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))] (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
...@@ -7708,38 +7718,39 @@ label: ...@@ -7708,38 +7718,39 @@ label:
{ {
case REG: case REG:
/* This is complicated. If the register is an arithmetic register /* This is complicated. If the register is an arithmetic register
we can just fall through to the REG+DISP case below. Otherwise we can just fall through to the REG+DISP case below. Otherwise
we have to use a combination of POST_INC and REG addressing... */ we have to use a combination of POST_INC and REG addressing... */
if (! arith_reg_operand (operands[1], SFmode)) if (! arith_reg_operand (operands[1], SFmode))
{ {
XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr); XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2])); insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
add_reg_note (insn, REG_INC, XEXP (addr, 0)); add_reg_note (insn, REG_INC, XEXP (addr, 0));
emit_insn (gen_movsf_ie (reg1, operands[1], operands[2])); emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
/* If we have modified the stack pointer, the value that we have /* If we have modified the stack pointer, the value that we have
read with post-increment might be modified by an interrupt, read with post-increment might be modified by an interrupt,
so write it back. */ so write it back. */
if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM) if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
emit_insn (gen_push_e (reg0)); emit_insn (gen_push_e (reg0));
else else
emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0), GEN_INT (-4))); emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
GEN_INT (-4)));
break; break;
} }
/* Fall through. */ /* Fall through. */
case PLUS: case PLUS:
emit_insn (gen_movsf_ie (reg0, operands[1], operands[2])); emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
operands[1] = copy_rtx (operands[1]); operands[1] = copy_rtx (operands[1]);
XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4); XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
emit_insn (gen_movsf_ie (reg1, operands[1], operands[2])); emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
break; break;
case POST_INC: case POST_INC:
insn = emit_insn (gen_movsf_ie (reg0, operands[1], operands[2])); insn = emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
add_reg_note (insn, REG_INC, XEXP (addr, 0)); add_reg_note (insn, REG_INC, XEXP (addr, 0));
insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2])); insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
add_reg_note (insn, REG_INC, XEXP (addr, 0)); add_reg_note (insn, REG_INC, XEXP (addr, 0));
break; break;
...@@ -7774,25 +7785,25 @@ label: ...@@ -7774,25 +7785,25 @@ label:
{ {
case REG: case REG:
/* This is complicated. If the register is an arithmetic register /* This is complicated. If the register is an arithmetic register
we can just fall through to the REG+DISP case below. Otherwise we can just fall through to the REG+DISP case below. Otherwise
we have to use a combination of REG and PRE_DEC addressing... */ we have to use a combination of REG and PRE_DEC addressing... */
if (! arith_reg_operand (operands[0], SFmode)) if (! arith_reg_operand (operands[0], SFmode))
{ {
emit_insn (gen_addsi3 (addr, addr, GEN_INT (4))); emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
emit_insn (gen_movsf_ie (operands[0], reg1, operands[2])); emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
operands[0] = copy_rtx (operands[0]); operands[0] = copy_rtx (operands[0]);
XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr); XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2])); insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
add_reg_note (insn, REG_INC, XEXP (addr, 0)); add_reg_note (insn, REG_INC, XEXP (addr, 0));
break; break;
} }
/* Fall through. */ /* Fall through. */
case PLUS: case PLUS:
/* Since REG+DISP addressing has already been decided upon by gcc /* Since REG+DISP addressing has already been decided upon by gcc
we can rely upon it having chosen an arithmetic register as the we can rely upon it having chosen an arithmetic register as the
register component of the address. Just emit the lower numbered register component of the address. Just emit the lower numbered
register first, to the lower address, then the higher numbered register first, to the lower address, then the higher numbered
register to the higher address. */ register to the higher address. */
...@@ -7801,9 +7812,9 @@ label: ...@@ -7801,9 +7812,9 @@ label:
operands[0] = copy_rtx (operands[0]); operands[0] = copy_rtx (operands[0]);
XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4); XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
emit_insn (gen_movsf_ie (operands[0], reg1, operands[2])); emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
break; break;
case PRE_DEC: case PRE_DEC:
/* This is easy. Output the word to go to the higher address /* This is easy. Output the word to go to the higher address
first (ie the word in the higher numbered register) then the first (ie the word in the higher numbered register) then the
...@@ -7815,7 +7826,7 @@ label: ...@@ -7815,7 +7826,7 @@ label:
insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2])); insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
add_reg_note (insn, REG_INC, XEXP (addr, 0)); add_reg_note (insn, REG_INC, XEXP (addr, 0));
break; break;
default: default:
/* FAIL; */ /* FAIL; */
debug_rtx (addr); debug_rtx (addr);
...@@ -7827,7 +7838,6 @@ label: ...@@ -7827,7 +7838,6 @@ label:
;; If the output is a register and the input is memory or a register, we have ;; If the output is a register and the input is memory or a register, we have
;; to be careful and see which word needs to be loaded first. ;; to be careful and see which word needs to be loaded first.
(define_split (define_split
[(set (match_operand:DF 0 "general_movdst_operand" "") [(set (match_operand:DF 0 "general_movdst_operand" "")
(match_operand:DF 1 "general_movsrc_operand" ""))] (match_operand:DF 1 "general_movsrc_operand" ""))]
...@@ -7912,7 +7922,6 @@ label: ...@@ -7912,7 +7922,6 @@ label:
;; fld%M1.p %m1, %0 ;; fld%M1.p %m1, %0
;; fst%M0.p %m0, %1" ;; fst%M0.p %m0, %1"
;; [(set_attr "type" "*,fload_media,fstore_media")]) ;; [(set_attr "type" "*,fload_media,fstore_media")])
(define_insn_and_split "movv2sf_i" (define_insn_and_split "movv2sf_i"
[(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf") [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
(match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))] (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
...@@ -7981,9 +7990,7 @@ label: ...@@ -7981,9 +7990,7 @@ label:
"&& reload_completed" "&& reload_completed"
[(const_int 0)] [(const_int 0)]
{ {
int i; for (int i = 0; i < 4/2; i++)
for (i = 0; i < 4/2; i++)
{ {
rtx x, y; rtx x, y;
...@@ -8022,11 +8029,9 @@ label: ...@@ -8022,11 +8029,9 @@ label:
"&& reload_completed" "&& reload_completed"
[(const_int 0)] [(const_int 0)]
{ {
int i; for (int i = 0; i < 16/2; i++)
for (i = 0; i < 16/2; i++)
{ {
rtx x,y; rtx x, y;
if (MEM_P (operands[0])) if (MEM_P (operands[0]))
x = adjust_address (operands[0], V2SFmode, x = adjust_address (operands[0], V2SFmode,
...@@ -8177,7 +8182,8 @@ label: ...@@ -8177,7 +8182,8 @@ label:
sts.l %1,%0 sts.l %1,%0
lds.l %1,%0 lds.l %1,%0
! move optimized away" ! move optimized away"
[(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil") [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
(set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*") (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
(set_attr_alternative "length" (set_attr_alternative "length"
[(const_int 2) [(const_int 2)
...@@ -8446,7 +8452,7 @@ label: ...@@ -8446,7 +8452,7 @@ label:
operands[2] = NULL_RTX; operands[2] = NULL_RTX;
break; break;
} }
if (operands[2] == NULL_RTX) if (operands[2] == NULL_RTX)
FAIL; FAIL;
...@@ -8645,12 +8651,11 @@ label: ...@@ -8645,12 +8651,11 @@ label:
[(set (pc) [(set (pc)
(if_then_else (if_then_else
(match_operator 3 "equality_comparison_operator" (match_operator 3 "equality_comparison_operator"
[(subreg:SI (zero_extract:DI (subreg:DI (match_operand:SI 1 [(subreg:SI
"extend_reg_operand" "") (zero_extract:DI
0) (subreg:DI (match_operand:SI 1 "extend_reg_operand" "") 0)
(const_int 1) (const_int 1)
(match_operand 2 (match_operand 2 "const_int_operand" "")) 0)
"const_int_operand" "")) 0)
(const_int 0)]) (const_int 0)])
(match_operand 0 "target_operand" "") (match_operand 0 "target_operand" "")
(pc))) (pc)))
...@@ -8670,13 +8675,12 @@ label: ...@@ -8670,13 +8675,12 @@ label:
; operand 2 is the maximum number of loop iterations ; operand 2 is the maximum number of loop iterations
; operand 3 is the number of levels of enclosed loops ; operand 3 is the number of levels of enclosed loops
; operand 4 is the label to jump to at the top of the loop ; operand 4 is the label to jump to at the top of the loop
(define_expand "doloop_end" (define_expand "doloop_end"
[(parallel [(set (pc) (if_then_else [(parallel [(set (pc)
(ne:SI (match_operand:SI 0 "" "") (if_then_else (ne:SI (match_operand:SI 0 "" "")
(const_int 1)) (const_int 1))
(label_ref (match_operand 4 "" "")) (label_ref (match_operand 4 "" ""))
(pc))) (pc)))
(set (match_dup 0) (set (match_dup 0)
(plus:SI (match_dup 0) (const_int -1))) (plus:SI (match_dup 0) (const_int -1)))
(clobber (reg:SI T_REG))]) (clobber (reg:SI T_REG))])
...@@ -8691,8 +8695,8 @@ label: ...@@ -8691,8 +8695,8 @@ label:
(define_insn_and_split "doloop_end_split" (define_insn_and_split "doloop_end_split"
[(set (pc) [(set (pc)
(if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0") (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
(const_int 1)) (const_int 1))
(label_ref (match_operand 1 "" "")) (label_ref (match_operand 1 "" ""))
(pc))) (pc)))
(set (match_operand:SI 0 "arith_reg_dest" "=r") (set (match_operand:SI 0 "arith_reg_dest" "=r")
...@@ -8708,8 +8712,7 @@ label: ...@@ -8708,8 +8712,7 @@ label:
(label_ref (match_dup 1)) (label_ref (match_dup 1))
(pc)))] (pc)))]
"" ""
[(set_attr "type" "cbranch")]) [(set_attr "type" "cbranch")])
;; ------------------------------------------------------------------------ ;; ------------------------------------------------------------------------
;; Jump and linkage insns ;; Jump and linkage insns
...@@ -8760,8 +8763,7 @@ label: ...@@ -8760,8 +8763,7 @@ label:
{ {
if (reload_in_progress || reload_completed) if (reload_in_progress || reload_completed)
FAIL; FAIL;
emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode, emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode, operands[0])));
operands[0])));
} }
DONE; DONE;
}) })
...@@ -8795,9 +8797,8 @@ label: ...@@ -8795,9 +8797,8 @@ label:
(set_attr "fp_set" "unknown")]) (set_attr "fp_set" "unknown")])
;; This is TBR relative jump instruction for SH2A architecture. ;; This is TBR relative jump instruction for SH2A architecture.
;; Its use is enabled assigning an attribute "function_vector" ;; Its use is enabled by assigning an attribute "function_vector"
;; and the vector number to a function during its declaration. ;; and the vector number to a function during its declaration.
(define_insn "calli_tbr_rel" (define_insn "calli_tbr_rel"
[(call (mem (match_operand:SI 0 "symbol_ref_operand" "")) [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
(match_operand 1 "" "")) (match_operand 1 "" ""))
...@@ -8819,7 +8820,6 @@ label: ...@@ -8819,7 +8820,6 @@ label:
(set_attr "fp_set" "unknown")]) (set_attr "fp_set" "unknown")])
;; This is a pc-rel call, using bsrf, for use with PIC. ;; This is a pc-rel call, using bsrf, for use with PIC.
(define_insn "calli_pcrel" (define_insn "calli_pcrel"
[(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
(match_operand 1 "" "")) (match_operand 1 "" ""))
...@@ -8931,7 +8931,6 @@ label: ...@@ -8931,7 +8931,6 @@ label:
;; This is TBR relative jump instruction for SH2A architecture. ;; This is TBR relative jump instruction for SH2A architecture.
;; Its use is enabled by assigning an attribute "function_vector" ;; Its use is enabled by assigning an attribute "function_vector"
;; and the vector number to a function during its declaration. ;; and the vector number to a function during its declaration.
(define_insn "call_valuei_tbr_rel" (define_insn "call_valuei_tbr_rel"
[(set (match_operand 0 "" "=rf") [(set (match_operand 0 "" "=rf")
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "")) (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
...@@ -9200,13 +9199,13 @@ label: ...@@ -9200,13 +9199,13 @@ label:
if (flag_pic) if (flag_pic)
{ {
if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func)) if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{ {
rtx reg = gen_reg_rtx (Pmode); rtx reg = gen_reg_rtx (Pmode);
emit_insn (gen_symGOTPLT2reg (reg, func)); emit_insn (gen_symGOTPLT2reg (reg, func));
func = reg; func = reg;
} }
else else
func = legitimize_pic_address (func, Pmode, 0); func = legitimize_pic_address (func, Pmode, 0);
} }
r0 = gen_rtx_REG (SImode, R0_REG); r0 = gen_rtx_REG (SImode, R0_REG);
...@@ -9798,14 +9797,14 @@ label: ...@@ -9798,14 +9797,14 @@ label:
if (flag_pic) if (flag_pic)
{ {
if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func)) if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{ {
rtx reg = gen_reg_rtx (Pmode); rtx reg = gen_reg_rtx (Pmode);
emit_insn (gen_symGOTPLT2reg (reg, func)); emit_insn (gen_symGOTPLT2reg (reg, func));
func = reg; func = reg;
} }
else else
func = legitimize_pic_address (func, Pmode, 0); func = legitimize_pic_address (func, Pmode, 0);
} }
r0 = gen_rtx_REG (SImode, R0_REG); r0 = gen_rtx_REG (SImode, R0_REG);
...@@ -9893,7 +9892,7 @@ label: ...@@ -9893,7 +9892,7 @@ label:
(match_operand:SI 0 "register_operand" "r")) (match_operand:SI 0 "register_operand" "r"))
(use (label_ref (match_operand 1 "" "")))] (use (label_ref (match_operand 1 "" "")))]
"TARGET_SH1" "TARGET_SH1"
"jmp @%0%#" "jmp @%0%#"
[(set_attr "needs_delay_slot" "yes") [(set_attr "needs_delay_slot" "yes")
(set_attr "type" "jump_ind")]) (set_attr "type" "jump_ind")])
...@@ -9917,7 +9916,6 @@ label: ...@@ -9917,7 +9916,6 @@ label:
;; Call subroutine returning any type. ;; Call subroutine returning any type.
;; ??? This probably doesn't work. ;; ??? This probably doesn't work.
(define_expand "untyped_call" (define_expand "untyped_call"
[(parallel [(call (match_operand 0 "" "") [(parallel [(call (match_operand 0 "" "")
(const_int 0)) (const_int 0))
...@@ -9925,11 +9923,9 @@ label: ...@@ -9925,11 +9923,9 @@ label:
(match_operand 2 "" "")])] (match_operand 2 "" "")])]
"(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA" "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
{ {
int i;
emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
for (i = 0; i < XVECLEN (operands[2], 0); i++) for (int i = 0; i < XVECLEN (operands[2], 0); i++)
{ {
rtx set = XVECEXP (operands[2], 0, i); rtx set = XVECEXP (operands[2], 0, i);
emit_move_insn (SET_DEST (set), SET_SRC (set)); emit_move_insn (SET_DEST (set), SET_SRC (set));
...@@ -9965,8 +9961,7 @@ label: ...@@ -9965,8 +9961,7 @@ label:
;; Load address of a label. This is only generated by the casesi expand, ;; Load address of a label. This is only generated by the casesi expand,
;; and by machine_dependent_reorg (fixing up fp moves). ;; and by machine_dependent_reorg (fixing up fp moves).
;; This must use unspec, because this only works for labels that are ;; This must use unspec, because this only works for labels that are
;; within range, ;; within range.
(define_insn "mova" (define_insn "mova"
[(set (reg:SI R0_REG) [(set (reg:SI R0_REG)
(unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))] (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
...@@ -10036,7 +10031,6 @@ label: ...@@ -10036,7 +10031,6 @@ label:
;; A helper for GOTaddr2picreg to finish up the initialization of the ;; A helper for GOTaddr2picreg to finish up the initialization of the
;; PIC register. ;; PIC register.
(define_expand "vxworks_picreg" (define_expand "vxworks_picreg"
[(set (reg:SI PIC_REG) [(set (reg:SI PIC_REG)
(const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC))) (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
...@@ -10096,7 +10090,6 @@ label: ...@@ -10096,7 +10090,6 @@ label:
;; op0 = op1 + r12 but hide it before reload completed. See the comment ;; op0 = op1 + r12 but hide it before reload completed. See the comment
;; in symGOT_load expand. ;; in symGOT_load expand.
(define_insn_and_split "chk_guard_add" (define_insn_and_split "chk_guard_add"
[(set (match_operand:SI 0 "register_operand" "=&r") [(set (match_operand:SI 0 "register_operand" "=&r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r") (unspec:SI [(match_operand:SI 1 "register_operand" "r")
...@@ -10262,8 +10255,11 @@ label: ...@@ -10262,8 +10255,11 @@ label:
"" ""
"") "")
;; -------------------------------------------------------------------------
;; TLS code generation. ;; TLS code generation.
;; ??? this should be a define_insn_and_split
;; FIXME: The multi-insn asm blocks should be converted to use
;; define_insn_and_split.
;; See the thread [PATCH/RFA] SH TLS support on gcc-patches ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html> ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
;; for details. ;; for details.
...@@ -10588,12 +10584,11 @@ label: ...@@ -10588,12 +10584,11 @@ label:
;;------------------------------------------------------------------------------ ;;------------------------------------------------------------------------------
;; case instruction for switch statements. ;; case instruction for switch statements.
;; Operand 0 is index ;; operand 0 is index
;; operand 1 is the minimum bound ;; operand 1 is the minimum bound
;; operand 2 is the maximum bound - minimum bound + 1 ;; operand 2 is the maximum bound - minimum bound + 1
;; operand 3 is CODE_LABEL for the table; ;; operand 3 is CODE_LABEL for the table;
;; operand 4 is the CODE_LABEL to go to if index out of range. ;; operand 4 is the CODE_LABEL to go to if index out of range.
(define_expand "casesi" (define_expand "casesi"
[(match_operand:SI 0 "arith_reg_operand" "") [(match_operand:SI 0 "arith_reg_operand" "")
(match_operand:SI 1 "arith_reg_operand" "") (match_operand:SI 1 "arith_reg_operand" "")
...@@ -10617,7 +10612,8 @@ label: ...@@ -10617,7 +10612,8 @@ label:
operands[2] = convert_modes (DImode, SImode, operands[2], 1); operands[2] = convert_modes (DImode, SImode, operands[2], 1);
test = gen_rtx_GT (VOIDmode, operands[1], operands[0]); test = gen_rtx_GT (VOIDmode, operands[1], operands[0]);
emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0], operands[4])); emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0],
operands[4]));
emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1])); emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
test = gen_rtx_GTU (VOIDmode, reg, operands[2]); test = gen_rtx_GTU (VOIDmode, reg, operands[2]);
emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4])); emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4]));
...@@ -10675,7 +10671,6 @@ label: ...@@ -10675,7 +10671,6 @@ label:
;; ??? reload might clobber r0 if we use it explicitly in the RTL before ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
;; reload; using a R0_REGS pseudo reg is likely to give poor code. ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload. ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
(define_insn "casesi_worker_0" (define_insn "casesi_worker_0"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "0,r") (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
...@@ -10823,8 +10818,8 @@ label: ...@@ -10823,8 +10818,8 @@ label:
(define_insn "casesi_load_media" (define_insn "casesi_load_media"
[(set (match_operand 0 "any_arith_reg_dest" "=r") [(set (match_operand 0 "any_arith_reg_dest" "=r")
(mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r") (mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "arith_reg_operand" "r") (match_operand:DI 2 "arith_reg_operand" "r")
(label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))] (label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
{ {
rtx diff_vec = PATTERN (next_real_insn (operands[3])); rtx diff_vec = PATTERN (next_real_insn (operands[3]));
...@@ -11263,7 +11258,6 @@ label: ...@@ -11263,7 +11258,6 @@ label:
;; around it. On the other hand, if a function returns the complement of ;; around it. On the other hand, if a function returns the complement of
;; a previous comparison result in the T bit, the xor #1,r0 approach might ;; a previous comparison result in the T bit, the xor #1,r0 approach might
;; lead to better code. ;; lead to better code.
(define_expand "movnegt" (define_expand "movnegt"
[(set (match_operand:SI 0 "arith_reg_dest" "") [(set (match_operand:SI 0 "arith_reg_dest" "")
(xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))] (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
...@@ -11419,7 +11413,7 @@ label: ...@@ -11419,7 +11413,7 @@ label:
;; Store negated T bit as all zeros or ones in a reg. ;; Store negated T bit as all zeros or ones in a reg.
;; Use the following sequence: ;; Use the following sequence:
;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
;; not Rn,Rn ! Rn = 0 - Rn ;; not Rn,Rn ! Rn = 0 - Rn
(define_split (define_split
[(set (match_operand:SI 0 "arith_reg_dest" "") [(set (match_operand:SI 0 "arith_reg_dest" "")
...@@ -11437,6 +11431,11 @@ label: ...@@ -11437,6 +11431,11 @@ label:
"" ""
[(const_int 0)]) [(const_int 0)])
;; Invert the T bit.
;; On SH2A we can use the nott insn. On anything else this must be done with
;; multiple insns like:
;; movt Rn
;; tst Rn,Rn
(define_insn_and_split "nott" (define_insn_and_split "nott"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(xor:SI (match_operand:SI 0 "t_reg_operand" "") (const_int 1)))] (xor:SI (match_operand:SI 0 "t_reg_operand" "") (const_int 1)))]
...@@ -11500,7 +11499,9 @@ label: ...@@ -11500,7 +11499,9 @@ label:
}) })
;; The *cset_zero patterns convert optimizations such as ;; The *cset_zero patterns convert optimizations such as
;; "if (test) x = 0;" to "x &= -(test == 0);" ;; "if (test) x = 0;"
;; to
;; "x &= -(test == 0);"
;; back to conditional branch sequences if zero-displacement branches ;; back to conditional branch sequences if zero-displacement branches
;; are enabled. ;; are enabled.
;; FIXME: These patterns can be removed when conditional execution patterns ;; FIXME: These patterns can be removed when conditional execution patterns
...@@ -11580,8 +11581,7 @@ label: ...@@ -11580,8 +11581,7 @@ label:
;; Instructions to cope with inline literal tables ;; Instructions to cope with inline literal tables
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
; 2 byte integer in line ;; 2 byte integer in line
(define_insn "consttable_2" (define_insn "consttable_2"
[(unspec_volatile [(match_operand:SI 0 "general_operand" "=g") [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
(match_operand 1 "" "")] (match_operand 1 "" "")]
...@@ -11595,8 +11595,7 @@ label: ...@@ -11595,8 +11595,7 @@ label:
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "in_delay_slot" "no")]) (set_attr "in_delay_slot" "no")])
; 4 byte integer in line ;; 4 byte integer in line
(define_insn "consttable_4" (define_insn "consttable_4"
[(unspec_volatile [(match_operand:SI 0 "general_operand" "=g") [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
(match_operand 1 "" "")] (match_operand 1 "" "")]
...@@ -11613,8 +11612,7 @@ label: ...@@ -11613,8 +11612,7 @@ label:
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "in_delay_slot" "no")]) (set_attr "in_delay_slot" "no")])
; 8 byte integer in line ;; 8 byte integer in line
(define_insn "consttable_8" (define_insn "consttable_8"
[(unspec_volatile [(match_operand:SI 0 "general_operand" "=g") [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
(match_operand 1 "" "")] (match_operand 1 "" "")]
...@@ -11628,8 +11626,7 @@ label: ...@@ -11628,8 +11626,7 @@ label:
[(set_attr "length" "8") [(set_attr "length" "8")
(set_attr "in_delay_slot" "no")]) (set_attr "in_delay_slot" "no")])
; 4 byte floating point ;; 4 byte floating point
(define_insn "consttable_sf" (define_insn "consttable_sf"
[(unspec_volatile [(match_operand:SF 0 "general_operand" "=g") [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
(match_operand 1 "" "")] (match_operand 1 "" "")]
...@@ -11647,8 +11644,7 @@ label: ...@@ -11647,8 +11644,7 @@ label:
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "in_delay_slot" "no")]) (set_attr "in_delay_slot" "no")])
; 8 byte floating point ;; 8 byte floating point
(define_insn "consttable_df" (define_insn "consttable_df"
[(unspec_volatile [(match_operand:DF 0 "general_operand" "=g") [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
(match_operand 1 "" "")] (match_operand 1 "" "")]
...@@ -11672,24 +11668,21 @@ label: ...@@ -11672,24 +11668,21 @@ label:
;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
;; here is too conservative. ;; here is too conservative.
; align to a two byte boundary ;; align to a two byte boundary
(define_expand "align_2" (define_expand "align_2"
[(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)] [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
"" ""
"") "")
; align to a four byte boundary ;; Align to a four byte boundary.
;; align_4 and align_log are instructions for the starts of loops, or ;; align_4 and align_log are instructions for the starts of loops, or
;; after unconditional branches, which may take up extra room. ;; after unconditional branches, which may take up extra room.
(define_expand "align_4" (define_expand "align_4"
[(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)] [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
"" ""
"") "")
; align to a cache line boundary ;; Align to a cache line boundary.
(define_insn "align_log" (define_insn "align_log"
[(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)] [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
"" ""
...@@ -11697,9 +11690,8 @@ label: ...@@ -11697,9 +11690,8 @@ label:
[(set_attr "length" "0") [(set_attr "length" "0")
(set_attr "in_delay_slot" "no")]) (set_attr "in_delay_slot" "no")])
; emitted at the end of the literal table, used to emit the ;; Emitted at the end of the literal table, used to emit the
; 32bit branch labels if needed. ;; 32bit branch labels if needed.
(define_insn "consttable_end" (define_insn "consttable_end"
[(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)] [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
"" ""
...@@ -11708,8 +11700,7 @@ label: ...@@ -11708,8 +11700,7 @@ label:
} }
[(set_attr "in_delay_slot" "no")]) [(set_attr "in_delay_slot" "no")])
; emitted at the end of the window in the literal table. ;; Emitted at the end of the window in the literal table.
(define_insn "consttable_window_end" (define_insn "consttable_window_end"
[(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)] [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
"" ""
...@@ -11836,7 +11827,8 @@ label: ...@@ -11836,7 +11827,8 @@ label:
sts fpscr,%0 sts fpscr,%0
sts.l fpscr,%0" sts.l fpscr,%0"
[(set_attr "length" "0,2,2,4,2,2,2,2,2") [(set_attr "length" "0,2,2,4,2,2,2,2,2")
(set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,mac_gp,fstore")]) (set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,
mac_gp,fstore")])
(define_peephole2 (define_peephole2
[(set (reg:PSI FPSCR_REG) [(set (reg:PSI FPSCR_REG)
...@@ -12158,7 +12150,8 @@ label: ...@@ -12158,7 +12150,8 @@ label:
{ {
if (TARGET_SH4 || TARGET_SH2A_SINGLE) if (TARGET_SH4 || TARGET_SH2A_SINGLE)
{ {
emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ())); emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1],
get_fpscr_rtx ()));
DONE; DONE;
} }
}) })
...@@ -12200,7 +12193,8 @@ label: ...@@ -12200,7 +12193,8 @@ label:
{ {
if (TARGET_SH4 || TARGET_SH2A_SINGLE) if (TARGET_SH4 || TARGET_SH2A_SINGLE)
{ {
emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ())); emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1],
get_fpscr_rtx ()));
DONE; DONE;
} }
}) })
...@@ -12958,8 +12952,12 @@ label: ...@@ -12958,8 +12952,12 @@ label:
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "fp_mode" "double")]) (set_attr "fp_mode" "double")])
;; Bit field extract patterns. These give better code for packed bitfields, ;; -------------------------------------------------------------------------
;; because they allow auto-increment addresses to be generated. ;; Bit field extract patterns.
;; -------------------------------------------------------------------------
;; These give better code for packed bitfields, because they allow
;; auto-increment addresses to be generated.
(define_expand "insv" (define_expand "insv"
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "") [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
...@@ -13356,7 +13354,6 @@ label: ...@@ -13356,7 +13354,6 @@ label:
return alt[which_alternative]; return alt[which_alternative];
} }
[(set_attr "length" "6,6")]) [(set_attr "length" "6,6")])
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
;; Peepholes ;; Peepholes
...@@ -13374,8 +13371,7 @@ label: ...@@ -13374,8 +13371,7 @@ label:
&& satisfies_constraint_Pso (operands[2]) && satisfies_constraint_Pso (operands[2])
&& REGNO (operands[0]) == REGNO (operands[3])" && REGNO (operands[0]) == REGNO (operands[3])"
[(set (match_dup 1) [(set (match_dup 1)
(ior:QI (match_dup 1) (ior:QI (match_dup 1) (match_dup 2)))]
(match_dup 2)))]
"") "")
;; This matches cases where the bit in a memory location is cleared. ;; This matches cases where the bit in a memory location is cleared.
...@@ -13391,13 +13387,11 @@ label: ...@@ -13391,13 +13387,11 @@ label:
&& satisfies_constraint_Psz (operands[2]) && satisfies_constraint_Psz (operands[2])
&& REGNO (operands[0]) == REGNO (operands[3])" && REGNO (operands[0]) == REGNO (operands[3])"
[(set (match_dup 1) [(set (match_dup 1)
(and:QI (match_dup 1) (and:QI (match_dup 1) (match_dup 2)))]
(match_dup 2)))]
"") "")
;; This matches cases where a stack pointer increment at the start of the ;; This matches cases where a stack pointer increment at the start of the
;; epilogue combines with a stack slot read loading the return value. ;; epilogue combines with a stack slot read loading the return value.
(define_peephole (define_peephole
[(set (match_operand:SI 0 "arith_reg_operand" "") [(set (match_operand:SI 0 "arith_reg_operand" "")
(mem:SI (match_operand:SI 1 "arith_reg_operand" ""))) (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
...@@ -13406,14 +13400,12 @@ label: ...@@ -13406,14 +13400,12 @@ label:
"mov.l @%1+,%0") "mov.l @%1+,%0")
;; See the comment on the dt combiner pattern above. ;; See the comment on the dt combiner pattern above.
(define_peephole (define_peephole
[(set (match_operand:SI 0 "arith_reg_operand" "=r") [(set (match_operand:SI 0 "arith_reg_operand" "=r")
(plus:SI (match_dup 0) (plus:SI (match_dup 0)
(const_int -1))) (const_int -1)))
(set (reg:SI T_REG) (set (reg:SI T_REG)
(eq:SI (match_dup 0) (eq:SI (match_dup 0) (const_int 0)))]
(const_int 0)))]
"TARGET_SH2" "TARGET_SH2"
"dt %0") "dt %0")
...@@ -13615,7 +13607,9 @@ label: ...@@ -13615,7 +13607,9 @@ label:
} }
[(set_attr "length" "4")]) [(set_attr "length" "4")])
;; -------------------------------------------------------------------------
;; Integer vector moves ;; Integer vector moves
;; -------------------------------------------------------------------------
(define_expand "movv8qi" (define_expand "movv8qi"
[(set (match_operand:V8QI 0 "general_movdst_operand" "") [(set (match_operand:V8QI 0 "general_movdst_operand" "")
...@@ -13784,7 +13778,9 @@ label: ...@@ -13784,7 +13778,9 @@ label:
(set_attr "length" "4,4,16,4,4") (set_attr "length" "4,4,16,4,4")
(set_attr "highpart" "depend")]) (set_attr "highpart" "depend")])
;; -------------------------------------------------------------------------
;; Multimedia Intrinsics ;; Multimedia Intrinsics
;; -------------------------------------------------------------------------
(define_insn "absv2si2" (define_insn "absv2si2"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r") [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
...@@ -13870,8 +13866,9 @@ label: ...@@ -13870,8 +13866,9 @@ label:
(define_insn "negcmpeqv8qi" (define_insn "negcmpeqv8qi"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r") [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(neg:V8QI (eq:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ") (neg:V8QI (eq:V8QI
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))] (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpeq.b %N1, %N2, %0" "mcmpeq.b %N1, %N2, %0"
[(set_attr "type" "mcmp_media") [(set_attr "type" "mcmp_media")
...@@ -13879,8 +13876,9 @@ label: ...@@ -13879,8 +13876,9 @@ label:
(define_insn "negcmpeqv2si" (define_insn "negcmpeqv2si"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r") [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(neg:V2SI (eq:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ") (neg:V2SI (eq:V2SI
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))] (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpeq.l %N1, %N2, %0" "mcmpeq.l %N1, %N2, %0"
[(set_attr "type" "mcmp_media") [(set_attr "type" "mcmp_media")
...@@ -13888,8 +13886,9 @@ label: ...@@ -13888,8 +13886,9 @@ label:
(define_insn "negcmpeqv4hi" (define_insn "negcmpeqv4hi"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(neg:V4HI (eq:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ") (neg:V4HI (eq:V4HI
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))] (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpeq.w %N1, %N2, %0" "mcmpeq.w %N1, %N2, %0"
[(set_attr "type" "mcmp_media") [(set_attr "type" "mcmp_media")
...@@ -13897,8 +13896,9 @@ label: ...@@ -13897,8 +13896,9 @@ label:
(define_insn "negcmpgtuv8qi" (define_insn "negcmpgtuv8qi"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r") [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(neg:V8QI (gtu:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ") (neg:V8QI (gtu:V8QI
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))] (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpgt.ub %N1, %N2, %0" "mcmpgt.ub %N1, %N2, %0"
[(set_attr "type" "mcmp_media") [(set_attr "type" "mcmp_media")
...@@ -13906,8 +13906,9 @@ label: ...@@ -13906,8 +13906,9 @@ label:
(define_insn "negcmpgtv2si" (define_insn "negcmpgtv2si"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r") [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(neg:V2SI (gt:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ") (neg:V2SI (gt:V2SI
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))] (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpgt.l %N1, %N2, %0" "mcmpgt.l %N1, %N2, %0"
[(set_attr "type" "mcmp_media") [(set_attr "type" "mcmp_media")
...@@ -13915,8 +13916,9 @@ label: ...@@ -13915,8 +13916,9 @@ label:
(define_insn "negcmpgtv4hi" (define_insn "negcmpgtv4hi"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(neg:V4HI (gt:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ") (neg:V4HI (gt:V4HI
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))] (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpgt.w %N1, %N2, %0" "mcmpgt.w %N1, %N2, %0"
[(set_attr "type" "mcmp_media") [(set_attr "type" "mcmp_media")
...@@ -13937,7 +13939,8 @@ label: ...@@ -13937,7 +13939,8 @@ label:
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_concat:V4HI (vec_concat:V4HI
(ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")) (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
(ss_truncate:V2HI (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))] (ss_truncate:V2HI
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcnvs.lw %N1, %N2, %0" "mcnvs.lw %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
...@@ -13946,7 +13949,8 @@ label: ...@@ -13946,7 +13949,8 @@ label:
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r") [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_concat:V8QI (vec_concat:V8QI
(ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")) (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
(ss_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))] (ss_truncate:V4QI
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcnvs.wb %N1, %N2, %0" "mcnvs.wb %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
...@@ -13955,7 +13959,8 @@ label: ...@@ -13955,7 +13959,8 @@ label:
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r") [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_concat:V8QI (vec_concat:V8QI
(us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")) (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
(us_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))] (us_truncate:V4QI
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcnvs.wub %N1, %N2, %0" "mcnvs.wub %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
...@@ -13964,8 +13969,8 @@ label: ...@@ -13964,8 +13969,8 @@ label:
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 3 "mextr_bit_offset" "i")) (match_operand:HI 3 "mextr_bit_offset" "i"))
(ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 4 "mextr_bit_offset" "i"))))] (match_operand:HI 4 "mextr_bit_offset" "i"))))]
"TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64" "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
{ {
static char templ[21]; static char templ[21];
...@@ -13979,8 +13984,8 @@ label: ...@@ -13979,8 +13984,8 @@ label:
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 3 "mextr_bit_offset" "i")) (match_operand:HI 3 "mextr_bit_offset" "i"))
(lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 4 "mextr_bit_offset" "i"))))] (match_operand:HI 4 "mextr_bit_offset" "i"))))]
"TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64" "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
{ {
static char templ[21]; static char templ[21];
...@@ -14627,7 +14632,7 @@ label: ...@@ -14627,7 +14632,7 @@ label:
(define_insn_and_split "mshfhi_l_di" (define_insn_and_split "mshfhi_l_di"
[(set (match_operand:DI 0 "arith_reg_dest" "=r,f") [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
(ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f") (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
(const_int 32)) (const_int 32))
(and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f") (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
(const_int -4294967296))))] (const_int -4294967296))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
...@@ -14651,7 +14656,7 @@ label: ...@@ -14651,7 +14656,7 @@ label:
(ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int -4294967296)) (const_int -4294967296))
(lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 32))))] (const_int 32))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mshfhi.l %N2, %N1, %0" "mshfhi.l %N2, %N1, %0"
[(set_attr "type" "arith_media")]) [(set_attr "type" "arith_media")])
...@@ -14679,7 +14684,7 @@ label: ...@@ -14679,7 +14684,7 @@ label:
(ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int 4294967295)) (const_int 4294967295))
(ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 32))))] (const_int 32))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mshflo.l %N1, %N2, %0" "mshflo.l %N1, %N2, %0"
...@@ -14689,7 +14694,7 @@ label: ...@@ -14689,7 +14694,7 @@ label:
(define_insn "*mshflo_l_di_rev" (define_insn "*mshflo_l_di_rev"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int 32)) (const_int 32))
(and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 4294967295))))] (const_int 4294967295))))]
...@@ -14702,7 +14707,7 @@ label: ...@@ -14702,7 +14707,7 @@ label:
(define_insn_and_split "*double_shori" (define_insn_and_split "*double_shori"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0") (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
(const_int 32)) (const_int 32))
(match_operand:DI 2 "const_int_operand" "n")))] (match_operand:DI 2 "const_int_operand" "n")))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)" && ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)"
...@@ -14718,14 +14723,12 @@ label: ...@@ -14718,14 +14723,12 @@ label:
} }
[(set_attr "highpart" "ignore")]) [(set_attr "highpart" "ignore")])
(define_insn "*mshflo_l_di_x" (define_insn "*mshflo_l_di_x"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand" (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
"rZ")) "rZ"))
(ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 32))))] (const_int 32))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mshflo.l %N1, %N2, %0" "mshflo.l %N1, %N2, %0"
[(set_attr "type" "arith_media") [(set_attr "type" "arith_media")
...@@ -14736,7 +14739,6 @@ label: ...@@ -14736,7 +14739,6 @@ label:
;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f") ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
(vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f") (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
(match_operand:SF 2 "register_operand" "rZ,f,f")))] (match_operand:SF 2 "register_operand" "rZ,f,f")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"@ "@
mshflo.l %N1, %N2, %0 mshflo.l %N1, %N2, %0
...@@ -14756,9 +14758,9 @@ label: ...@@ -14756,9 +14758,9 @@ label:
(define_insn "*mshflo_l_di_x_rev" (define_insn "*mshflo_l_di_x_rev"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int 32)) (const_int 32))
(zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))] (zero_extend:DI
(match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mshflo.l %N2, %N1, %0" "mshflo.l %N2, %N1, %0"
[(set_attr "type" "arith_media") [(set_attr "type" "arith_media")
...@@ -14888,7 +14890,9 @@ label: ...@@ -14888,7 +14890,9 @@ label:
[(set_attr "type" "mcmp_media") [(set_attr "type" "mcmp_media")
(set_attr "highpart" "depend")]) (set_attr "highpart" "depend")])
;; -------------------------------------------------------------------------
;; Floating Point Intrinsics ;; Floating Point Intrinsics
;; -------------------------------------------------------------------------
(define_insn "fcosa_s" (define_insn "fcosa_s"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
...@@ -14993,10 +14997,9 @@ label: ...@@ -14993,10 +14997,9 @@ label:
(define_insn_and_split "*ldhi_q_comb0" (define_insn_and_split "*ldhi_q_comb0"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(zero_extract:DI (zero_extract:DI
(mem:DI (plus:SI (ior:SI (plus:SI (match_operand:SI 1 (mem:DI (plus:SI (ior:SI (plus:SI
"register_operand" "r") (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 (match_operand:SI 2 "ua_offset" "I06"))
"ua_offset" "I06"))
(const_int 7)) (const_int 7))
(const_int -7))) (const_int -7)))
(plus:SI (and:SI (match_dup 1) (const_int 7)) (plus:SI (and:SI (match_dup 1) (const_int 7))
...@@ -15015,14 +15018,13 @@ label: ...@@ -15015,14 +15018,13 @@ label:
(define_insn_and_split "*ldhi_q_comb1" (define_insn_and_split "*ldhi_q_comb1"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(zero_extract:DI (zero_extract:DI
(mem:DI (plus:SI (ior:SI (plus:SI (match_operand:SI 1 (mem:DI (plus:SI (ior:SI (plus:SI
"register_operand" "r") (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 (match_operand:SI 2 "ua_offset" "I06"))
"ua_offset" "I06"))
(const_int 7)) (const_int 7))
(const_int -7))) (const_int -7)))
(plus:SI (and:SI (plus:SI (match_dup 1) (match_operand:SI 3 (plus:SI (and:SI (plus:SI (match_dup 1)
"ua_offset" "I06")) (match_operand:SI 3 "ua_offset" "I06"))
(const_int 7)) (const_int 7))
(const_int 1)) (const_int 1))
(const_int 0)))] (const_int 0)))]
...@@ -15129,10 +15131,9 @@ label: ...@@ -15129,10 +15131,9 @@ label:
(define_insn_and_split "*sthi_q_comb0" (define_insn_and_split "*sthi_q_comb0"
[(set (zero_extract:DI [(set (zero_extract:DI
(mem:DI (plus:SI (ior:SI (plus:SI (match_operand:SI 0 (mem:DI (plus:SI (ior:SI (plus:SI
"register_operand" "r") (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "ua_offset" (match_operand:SI 1 "ua_offset" "I06"))
"I06"))
(const_int 7)) (const_int 7))
(const_int -7))) (const_int -7)))
(plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1)) (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
...@@ -15150,10 +15151,9 @@ label: ...@@ -15150,10 +15151,9 @@ label:
(define_insn_and_split "*sthi_q_comb1" (define_insn_and_split "*sthi_q_comb1"
[(set (zero_extract:DI [(set (zero_extract:DI
(mem:DI (plus:SI (ior:SI (plus:SI (match_operand:SI 0 (mem:DI (plus:SI (ior:SI (plus:SI
"register_operand" "r") (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "ua_offset" (match_operand:SI 1 "ua_offset" "I06"))
"I06"))
(const_int 7)) (const_int 7))
(const_int -7))) (const_int -7)))
(plus:SI (and:SI (plus:SI (match_dup 0) (plus:SI (and:SI (plus:SI (match_dup 0)
...@@ -15219,10 +15219,10 @@ label: ...@@ -15219,10 +15219,10 @@ label:
(mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r") (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "ua_offset" "I06")) (match_operand:SI 1 "ua_offset" "I06"))
(const_int -8))) (const_int -8)))
(minus:SI (const_int 8) (and:SI (plus:SI (match_dup 0) (minus:SI (const_int 8)
(match_operand:SI 2 (and:SI (plus:SI (match_dup 0)
"ua_offset" "I06")) (match_operand:SI 2 "ua_offset" "I06"))
(const_int 7))) (const_int 7)))
(and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7))) (and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7)))
(match_operand:DI 3 "arith_reg_operand" "r"))] (match_operand:DI 3 "arith_reg_operand" "r"))]
"TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])" "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
...@@ -15411,8 +15411,8 @@ label: ...@@ -15411,8 +15411,8 @@ label:
;; implementation of __builtin_prefetch for VxWorks RTPs. ;; implementation of __builtin_prefetch for VxWorks RTPs.
(define_expand "prefetch" (define_expand "prefetch"
[(prefetch (match_operand 0 "address_operand" "") [(prefetch (match_operand 0 "address_operand" "")
(match_operand:SI 1 "const_int_operand" "") (match_operand:SI 1 "const_int_operand" "")
(match_operand:SI 2 "const_int_operand" ""))] (match_operand:SI 2 "const_int_operand" ""))]
"(TARGET_SH2A || TARGET_SH3 || TARGET_SH5) "(TARGET_SH2A || TARGET_SH3 || TARGET_SH5)
&& (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)") && (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)")
...@@ -15426,12 +15426,12 @@ label: ...@@ -15426,12 +15426,12 @@ label:
(define_insn "*prefetch_media" (define_insn "*prefetch_media"
[(prefetch (match_operand:QI 0 "address_operand" "p") [(prefetch (match_operand:QI 0 "address_operand" "p")
(match_operand:SI 1 "const_int_operand" "n") (match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))] (match_operand:SI 2 "const_int_operand" "n"))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
{ {
operands[0] = gen_rtx_MEM (QImode, operands[0]); operands[0] = gen_rtx_MEM (QImode, operands[0]);
output_asm_insn ("ld%M0.b %m0,r63", operands); output_asm_insn ("ld%M0.b %m0,r63", operands);
return ""; return "";
} }
[(set_attr "type" "other")]) [(set_attr "type" "other")])
...@@ -15453,7 +15453,7 @@ label: ...@@ -15453,7 +15453,7 @@ label:
xops[0] = operands[0]; xops[0] = operands[0];
xops[1] = const0_rtx; xops[1] = const0_rtx;
} }
output_asm_insn ("alloco %0, %1", xops); output_asm_insn ("alloco %0, %1", xops);
return ""; return "";
} }
[(set_attr "type" "other")]) [(set_attr "type" "other")])
...@@ -15471,7 +15471,9 @@ label: ...@@ -15471,7 +15471,9 @@ label:
FAIL; FAIL;
}) })
; Stack Protector Patterns ;; -------------------------------------------------------------------------
;; Stack Protector Patterns
;; -------------------------------------------------------------------------
(define_expand "stack_protect_set" (define_expand "stack_protect_set"
[(set (match_operand 0 "memory_operand" "") [(set (match_operand 0 "memory_operand" "")
...@@ -15493,7 +15495,7 @@ label: ...@@ -15493,7 +15495,7 @@ label:
(define_insn "stack_protect_set_si" (define_insn "stack_protect_set_si"
[(set (match_operand:SI 0 "memory_operand" "=m") [(set (match_operand:SI 0 "memory_operand" "=m")
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:SI 2 "=&r") (const_int 0))] (set (match_scratch:SI 2 "=&r") (const_int 0))]
"!TARGET_SHMEDIA" "!TARGET_SHMEDIA"
{ {
...@@ -15506,7 +15508,7 @@ label: ...@@ -15506,7 +15508,7 @@ label:
(define_insn "stack_protect_set_si_media" (define_insn "stack_protect_set_si_media"
[(set (match_operand:SI 0 "memory_operand" "=m") [(set (match_operand:SI 0 "memory_operand" "=m")
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:SI 2 "=&r") (const_int 0))] (set (match_scratch:SI 2 "=&r") (const_int 0))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
{ {
...@@ -15519,7 +15521,7 @@ label: ...@@ -15519,7 +15521,7 @@ label:
(define_insn "stack_protect_set_di_media" (define_insn "stack_protect_set_di_media"
[(set (match_operand:DI 0 "memory_operand" "=m") [(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET)) (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:DI 2 "=&r") (const_int 0))] (set (match_scratch:DI 2 "=&r") (const_int 0))]
"TARGET_SHMEDIA64" "TARGET_SHMEDIA64"
{ {
...@@ -15546,13 +15548,13 @@ label: ...@@ -15546,13 +15548,13 @@ label:
{ {
emit_insn (gen_stack_protect_test_di_media (tmp, operands[0], emit_insn (gen_stack_protect_test_di_media (tmp, operands[0],
operands[1])); operands[1]));
emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2])); emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2]));
} }
else else
{ {
emit_insn (gen_stack_protect_test_si_media (tmp, operands[0], emit_insn (gen_stack_protect_test_si_media (tmp, operands[0],
operands[1])); operands[1]));
emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2])); emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2]));
} }
} }
else else
...@@ -15566,7 +15568,7 @@ label: ...@@ -15566,7 +15568,7 @@ label:
(define_insn "stack_protect_test_si" (define_insn "stack_protect_test_si"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(unspec:SI [(match_operand:SI 0 "memory_operand" "m") (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
(match_operand:SI 1 "memory_operand" "m")] (match_operand:SI 1 "memory_operand" "m")]
UNSPEC_SP_TEST)) UNSPEC_SP_TEST))
(set (match_scratch:SI 2 "=&r") (const_int 0)) (set (match_scratch:SI 2 "=&r") (const_int 0))
...@@ -15584,7 +15586,7 @@ label: ...@@ -15584,7 +15586,7 @@ label:
(define_insn "stack_protect_test_si_media" (define_insn "stack_protect_test_si_media"
[(set (match_operand:SI 0 "register_operand" "=&r") [(set (match_operand:SI 0 "register_operand" "=&r")
(unspec:SI [(match_operand:SI 1 "memory_operand" "m") (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
(match_operand:SI 2 "memory_operand" "m")] (match_operand:SI 2 "memory_operand" "m")]
UNSPEC_SP_TEST)) UNSPEC_SP_TEST))
(set (match_scratch:SI 3 "=&r") (const_int 0))] (set (match_scratch:SI 3 "=&r") (const_int 0))]
...@@ -15600,7 +15602,7 @@ label: ...@@ -15600,7 +15602,7 @@ label:
(define_insn "stack_protect_test_di_media" (define_insn "stack_protect_test_di_media"
[(set (match_operand:DI 0 "register_operand" "=&r") [(set (match_operand:DI 0 "register_operand" "=&r")
(unspec:DI [(match_operand:DI 1 "memory_operand" "m") (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
(match_operand:DI 2 "memory_operand" "m")] (match_operand:DI 2 "memory_operand" "m")]
UNSPEC_SP_TEST)) UNSPEC_SP_TEST))
(set (match_scratch:DI 3 "=&r") (const_int 0))] (set (match_scratch:DI 3 "=&r") (const_int 0))]
...@@ -15614,4 +15616,8 @@ label: ...@@ -15614,4 +15616,8 @@ label:
[(set_attr "type" "other") [(set_attr "type" "other")
(set_attr "length" "16")]) (set_attr "length" "16")])
;; -------------------------------------------------------------------------
;; Atomic operations
;; -------------------------------------------------------------------------
(include "sync.md") (include "sync.md")
gcc/config/sh/sh4-300.md
...@@ -35,26 +35,21 @@ ...@@ -35,26 +35,21 @@
;; Since SH4 is a dual issue machine,it is as if there are two ;; Since SH4 is a dual issue machine,it is as if there are two
;; units so that any insn can be processed by either one ;; units so that any insn can be processed by either one
;; of the decoding unit. ;; of the decoding unit.
(define_cpu_unit "sh4_300_pipe_01,sh4_300_pipe_02" "sh4_300_inst_pipeline") (define_cpu_unit "sh4_300_pipe_01,sh4_300_pipe_02" "sh4_300_inst_pipeline")
;; The floating point units. ;; The floating point units.
(define_cpu_unit "sh4_300_fpt,sh4_300_fpu,sh4_300_fds" "sh4_300_fpu_pipe") (define_cpu_unit "sh4_300_fpt,sh4_300_fpu,sh4_300_fds" "sh4_300_fpu_pipe")
;; integer multiplier unit ;; integer multiplier unit
(define_cpu_unit "sh4_300_mul" "sh4_300_inst_pipeline") (define_cpu_unit "sh4_300_mul" "sh4_300_inst_pipeline")
;; LS unit ;; LS unit
(define_cpu_unit "sh4_300_ls" "sh4_300_inst_pipeline") (define_cpu_unit "sh4_300_ls" "sh4_300_inst_pipeline")
;; The address calculator used for branch instructions. ;; The address calculator used for branch instructions.
;; This will be reserved after "issue" of branch instructions ;; This will be reserved after "issue" of branch instructions
;; and this is to make sure that no two branch instructions ;; and this is to make sure that no two branch instructions
;; can be issued in parallel. ;; can be issued in parallel.
(define_cpu_unit "sh4_300_br" "sh4_300_inst_pipeline") (define_cpu_unit "sh4_300_br" "sh4_300_inst_pipeline")
;; ---------------------------------------------------- ;; ----------------------------------------------------
...@@ -85,7 +80,6 @@ ...@@ -85,7 +80,6 @@
"sh4_300_issue+sh4_300_mul") "sh4_300_issue+sh4_300_mul")
;; Instructions without specific resource requirements with latency 1. ;; Instructions without specific resource requirements with latency 1.
(define_insn_reservation "sh4_300_simple_arith" 1 (define_insn_reservation "sh4_300_simple_arith" 1
(and (eq_attr "pipe_model" "sh4_300") (and (eq_attr "pipe_model" "sh4_300")
(eq_attr "type" "mt_group,arith,dyn_shift,prset")) (eq_attr "type" "mt_group,arith,dyn_shift,prset"))
...@@ -153,7 +147,6 @@ ...@@ -153,7 +147,6 @@
;; or likely and likely not predicted, we might want to fill the delay slot. ;; or likely and likely not predicted, we might want to fill the delay slot.
;; However, there appears to be no machinery to make the compiler ;; However, there appears to be no machinery to make the compiler
;; recognize these scenarios. ;; recognize these scenarios.
(define_insn_reservation "sh4_300_branch" 1 (define_insn_reservation "sh4_300_branch" 1
(and (eq_attr "pipe_model" "sh4_300") (and (eq_attr "pipe_model" "sh4_300")
(eq_attr "type" "cbranch,jump,return,jump_ind")) (eq_attr "type" "cbranch,jump,return,jump_ind"))
...@@ -169,8 +162,11 @@ ...@@ -169,8 +162,11 @@
;; Group: CO ;; Group: CO
;; Latency: 1-5 ;; Latency: 1-5
;; Issue Rate: 1 ;; Issue Rate: 1
;; cwb is used for the sequence
;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2 ;; ocbwb @%0
;; extu.w %0,%2
;; or %1,%2
;; mov.l %0,@%2
;; This description is likely inexact, but this pattern should not actually ;; This description is likely inexact, but this pattern should not actually
;; appear when compiling for sh4-300; we should use isbi instead. ;; appear when compiling for sh4-300; we should use isbi instead.
;; If a -mtune option is added later, we should use the icache array ;; If a -mtune option is added later, we should use the icache array
...@@ -197,7 +193,6 @@ ...@@ -197,7 +193,6 @@
;; since there are no instructions that contend for memory access early. ;; since there are no instructions that contend for memory access early.
;; We could, of course, provide exact scheduling information for specific ;; We could, of course, provide exact scheduling information for specific
;; sfuncs, if that should prove useful. ;; sfuncs, if that should prove useful.
(define_insn_reservation "sh4_300_call" 16 (define_insn_reservation "sh4_300_call" 16
(and (eq_attr "pipe_model" "sh4_300") (and (eq_attr "pipe_model" "sh4_300")
(eq_attr "type" "call,sfunc")) (eq_attr "type" "call,sfunc"))
...@@ -265,7 +260,6 @@ ...@@ -265,7 +260,6 @@
(eq_attr "type" "dfdiv")) (eq_attr "type" "dfdiv"))
"sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*31") "sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*31")
;; ??? We don't really want these for sh4-300. ;; ??? We don't really want these for sh4-300.
;; this pattern itself is likely to finish in 3 cycles, but also ;; this pattern itself is likely to finish in 3 cycles, but also
;; to disrupt branch prediction for taken branches for the following ;; to disrupt branch prediction for taken branches for the following
......
gcc/config/sh/sh4.md
...@@ -41,35 +41,29 @@ ...@@ -41,35 +41,29 @@
;; Two automata are defined to reduce number of states ;; Two automata are defined to reduce number of states
;; which a single large automaton will have. (Factoring) ;; which a single large automaton will have. (Factoring)
(define_automaton "inst_pipeline,fpu_pipe") (define_automaton "inst_pipeline,fpu_pipe")
;; This unit is basically the decode unit of the processor. ;; This unit is basically the decode unit of the processor.
;; Since SH4 is a dual issue machine,it is as if there are two ;; Since SH4 is a dual issue machine,it is as if there are two
;; units so that any insn can be processed by either one ;; units so that any insn can be processed by either one
;; of the decoding unit. ;; of the decoding unit.
(define_cpu_unit "pipe_01,pipe_02" "inst_pipeline") (define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
;; The fixed point arithmetic calculator(?? EX Unit). ;; The fixed point arithmetic calculator(?? EX Unit).
(define_cpu_unit "int" "inst_pipeline") (define_cpu_unit "int" "inst_pipeline")
;; f1_1 and f1_2 are floating point units.Actually there is ;; f1_1 and f1_2 are floating point units.Actually there is
;; a f1 unit which can overlap with other f1 unit but ;; a f1 unit which can overlap with other f1 unit but
;; not another F1 unit.It is as though there were two ;; not another F1 unit.It is as though there were two
;; f1 units. ;; f1 units.
(define_cpu_unit "f1_1,f1_2" "fpu_pipe") (define_cpu_unit "f1_1,f1_2" "fpu_pipe")
;; The floating point units (except FS - F2 always precedes it.) ;; The floating point units (except FS - F2 always precedes it.)
(define_cpu_unit "F0,F1,F2,F3" "fpu_pipe") (define_cpu_unit "F0,F1,F2,F3" "fpu_pipe")
;; This is basically the MA unit of SH4 ;; This is basically the MA unit of SH4
;; used in LOAD/STORE pipeline. ;; used in LOAD/STORE pipeline.
(define_cpu_unit "memory" "inst_pipeline") (define_cpu_unit "memory" "inst_pipeline")
;; However, there are LS group insns that don't use it, even ones that ;; However, there are LS group insns that don't use it, even ones that
...@@ -85,12 +79,10 @@ ...@@ -85,12 +79,10 @@
;; ---------------------------------------------------- ;; ----------------------------------------------------
;; This reservation is to simplify the dual issue description. ;; This reservation is to simplify the dual issue description.
(define_reservation "issue" "pipe_01|pipe_02") (define_reservation "issue" "pipe_01|pipe_02")
;; This is to express the locking of D stage. ;; This is to express the locking of D stage.
;; Note that the issue of a CO group insn also effectively locks the D stage. ;; Note that the issue of a CO group insn also effectively locks the D stage.
(define_reservation "d_lock" "pipe_01+pipe_02") (define_reservation "d_lock" "pipe_01+pipe_02")
;; Every FE instruction but fipr / ftrv starts with issue and this. ;; Every FE instruction but fipr / ftrv starts with issue and this.
...@@ -98,12 +90,10 @@ ...@@ -98,12 +90,10 @@
;; This is to simplify description where F1,F2,FS ;; This is to simplify description where F1,F2,FS
;; are used simultaneously. ;; are used simultaneously.
(define_reservation "fpu" "F1+F2") (define_reservation "fpu" "F1+F2")
;; This is to highlight the fact that f1 ;; This is to highlight the fact that f1
;; cannot overlap with F1. ;; cannot overlap with F1.
(exclusion_set "f1_1,f1_2" "F1") (exclusion_set "f1_1,f1_2" "F1")
(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing") (define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
...@@ -113,14 +103,12 @@ ...@@ -113,14 +103,12 @@
;; for one cycle. ;; for one cycle.
;; Group: MT ;; Group: MT
(define_insn_reservation "reg_mov" 0 (define_insn_reservation "reg_mov" 0
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "move")) (eq_attr "type" "move"))
"issue") "issue")
;; Group: LS ;; Group: LS
(define_insn_reservation "freg_mov" 0 (define_insn_reservation "freg_mov" 0
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fmove")) (eq_attr "type" "fmove"))
...@@ -145,7 +133,6 @@ ...@@ -145,7 +133,6 @@
;; Group: MT ;; Group: MT
;; Latency: 1 ;; Latency: 1
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "mt" 1 (define_insn_reservation "mt" 1
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mt_group")) (eq_attr "type" "mt_group"))
...@@ -155,7 +142,6 @@ ...@@ -155,7 +142,6 @@
;; Group: EX ;; Group: EX
;; Latency: 1 ;; Latency: 1
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "sh4_simple_arith" 1 (define_insn_reservation "sh4_simple_arith" 1
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "insn_class" "ex_group")) (eq_attr "insn_class" "ex_group"))
...@@ -178,7 +164,6 @@ ...@@ -178,7 +164,6 @@
;; Group: LS ;; Group: LS
;; Latency: 2 ;; Latency: 2
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "sh4_load" 2 (define_insn_reservation "sh4_load" 2
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "load,pcload")) (eq_attr "type" "load,pcload"))
...@@ -220,7 +205,6 @@ ...@@ -220,7 +205,6 @@
;; Group: LS ;; Group: LS
;; Latency: 1 ;; Latency: 1
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "sh4_gp_fpul" 1 (define_insn_reservation "sh4_gp_fpul" 1
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "gp_fpul")) (eq_attr "type" "gp_fpul"))
...@@ -230,7 +214,6 @@ ...@@ -230,7 +214,6 @@
;; Group: LS ;; Group: LS
;; Latency: 3 ;; Latency: 3
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "sh4_fpul_gp" 3 (define_insn_reservation "sh4_fpul_gp" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fpul_gp")) (eq_attr "type" "fpul_gp"))
...@@ -246,7 +229,6 @@ ...@@ -246,7 +229,6 @@
;; ??? If the branch is likely, we might want to fill the delay slot; ;; ??? If the branch is likely, we might want to fill the delay slot;
;; if the branch is likely, but not very likely, should we pretend to use ;; if the branch is likely, but not very likely, should we pretend to use
;; a resource that CO instructions use, to get a pairable delay slot insn? ;; a resource that CO instructions use, to get a pairable delay slot insn?
(define_insn_reservation "sh4_branch" 1 (define_insn_reservation "sh4_branch" 1
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "cbranch,jump")) (eq_attr "type" "cbranch,jump"))
...@@ -258,7 +240,6 @@ ...@@ -258,7 +240,6 @@
;; Issue Rate: 2 ;; Issue Rate: 2
;; ??? Scheduling happens before branch shortening, and hence jmp and braf ;; ??? Scheduling happens before branch shortening, and hence jmp and braf
;; can't be distinguished from bra for the "jump" pattern. ;; can't be distinguished from bra for the "jump" pattern.
(define_insn_reservation "sh4_return" 3 (define_insn_reservation "sh4_return" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "return,jump_ind")) (eq_attr "type" "return,jump_ind"))
...@@ -270,7 +251,6 @@ ...@@ -270,7 +251,6 @@
;; Issue Rate: 5 ;; Issue Rate: 5
;; this instruction can be executed in any of the pipelines ;; this instruction can be executed in any of the pipelines
;; and blocks the pipeline for next 4 stages. ;; and blocks the pipeline for next 4 stages.
(define_insn_reservation "sh4_return_from_exp" 5 (define_insn_reservation "sh4_return_from_exp" 5
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "rte")) (eq_attr "type" "rte"))
...@@ -280,8 +260,11 @@ ...@@ -280,8 +260,11 @@
;; Group: CO ;; Group: CO
;; Latency: 1-5 ;; Latency: 1-5
;; Issue Rate: 1 ;; Issue Rate: 1
;; cwb is used for the sequence
;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2 ;; ocbwb @%0
;; extu.w %0,%2
;; or %1,%2
;; mov.l %0,@%2
;; ocbwb on its own would be "d_lock,nothing,memory*5" ;; ocbwb on its own would be "d_lock,nothing,memory*5"
(define_insn_reservation "ocbwb" 6 (define_insn_reservation "ocbwb" 6
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
...@@ -298,7 +281,6 @@ ...@@ -298,7 +281,6 @@
;; or when we are doing a function call - and we don't do inter-function ;; or when we are doing a function call - and we don't do inter-function
;; scheduling. For the function call case, it's really best that we end with ;; scheduling. For the function call case, it's really best that we end with
;; something that models an rts. ;; something that models an rts.
(define_insn_reservation "sh4_lds_to_pr" 3 (define_insn_reservation "sh4_lds_to_pr" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "prset") ) (eq_attr "type" "prset") )
...@@ -311,7 +293,6 @@ ...@@ -311,7 +293,6 @@
;; since there are no instructions that contend for memory access early. ;; since there are no instructions that contend for memory access early.
;; We could, of course, provide exact scheduling information for specific ;; We could, of course, provide exact scheduling information for specific
;; sfuncs, if that should prove useful. ;; sfuncs, if that should prove useful.
(define_insn_reservation "sh4_call" 16 (define_insn_reservation "sh4_call" 16
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "call,sfunc")) (eq_attr "type" "call,sfunc"))
...@@ -322,7 +303,6 @@ ...@@ -322,7 +303,6 @@
;; Latency: 3 ;; Latency: 3
;; Issue Rate: 2 ;; Issue Rate: 2
;; The SX unit is blocked for last 2 cycles. ;; The SX unit is blocked for last 2 cycles.
(define_insn_reservation "ldsmem_to_pr" 3 (define_insn_reservation "ldsmem_to_pr" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "pload")) (eq_attr "type" "pload"))
...@@ -333,7 +313,6 @@ ...@@ -333,7 +313,6 @@
;; Latency: 2 ;; Latency: 2
;; Issue Rate: 2 ;; Issue Rate: 2
;; The SX unit in second and third cycles. ;; The SX unit in second and third cycles.
(define_insn_reservation "sts_from_pr" 2 (define_insn_reservation "sts_from_pr" 2
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "prget")) (eq_attr "type" "prget"))
...@@ -343,7 +322,6 @@ ...@@ -343,7 +322,6 @@
;; Group: CO ;; Group: CO
;; Latency: 2 ;; Latency: 2
;; Issue Rate: 2 ;; Issue Rate: 2
(define_insn_reservation "sh4_prstore_mem" 2 (define_insn_reservation "sh4_prstore_mem" 2
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "pstore")) (eq_attr "type" "pstore"))
...@@ -354,7 +332,6 @@ ...@@ -354,7 +332,6 @@
;; Latency: 4 ;; Latency: 4
;; Issue Rate: 1 ;; Issue Rate: 1
;; F1 is blocked for last three cycles. ;; F1 is blocked for last three cycles.
(define_insn_reservation "fpscr_load" 4 (define_insn_reservation "fpscr_load" 4
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "gp_fpscr")) (eq_attr "type" "gp_fpscr"))
...@@ -366,7 +343,6 @@ ...@@ -366,7 +343,6 @@
;; Latency to update Rn is 1 and latency to update FPSCR is 4 ;; Latency to update Rn is 1 and latency to update FPSCR is 4
;; Issue Rate: 1 ;; Issue Rate: 1
;; F1 is blocked for last three cycles. ;; F1 is blocked for last three cycles.
(define_insn_reservation "fpscr_load_mem" 4 (define_insn_reservation "fpscr_load_mem" 4
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mem_fpscr")) (eq_attr "type" "mem_fpscr"))
...@@ -377,7 +353,6 @@ ...@@ -377,7 +353,6 @@
;; Group: CO ;; Group: CO
;; Latency: 4 / 4 ;; Latency: 4 / 4
;; Issue Rate: 2 ;; Issue Rate: 2
(define_insn_reservation "multi" 4 (define_insn_reservation "multi" 4
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "smpy,dmpy")) (eq_attr "type" "smpy,dmpy"))
...@@ -387,7 +362,6 @@ ...@@ -387,7 +362,6 @@
;; Group: CO ;; Group: CO
;; Latency: 3 ;; Latency: 3
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "sh4_mac_gp" 3 (define_insn_reservation "sh4_mac_gp" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mac_gp,gp_mac,mem_mac")) (eq_attr "type" "mac_gp,gp_mac,mem_mac"))
...@@ -399,7 +373,6 @@ ...@@ -399,7 +373,6 @@
;; Group: FE ;; Group: FE
;; Latency: 3/4 ;; Latency: 3/4
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "fp_arith" 3 (define_insn_reservation "fp_arith" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fp,fp_cmp")) (eq_attr "type" "fp,fp_cmp"))
...@@ -424,7 +397,6 @@ ...@@ -424,7 +397,6 @@
;; Latency: 12/13 (FDIV); 11/12 (FSQRT) ;; Latency: 12/13 (FDIV); 11/12 (FSQRT)
;; Issue Rate: 1 ;; Issue Rate: 1
;; We describe fdiv here; fsqrt is actually one cycle faster. ;; We describe fdiv here; fsqrt is actually one cycle faster.
(define_insn_reservation "fp_div" 12 (define_insn_reservation "fp_div" 12
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fdiv")) (eq_attr "type" "fdiv"))
...@@ -435,7 +407,6 @@ ...@@ -435,7 +407,6 @@
;; Group: FE ;; Group: FE
;; Latency: (3,4)/5 ;; Latency: (3,4)/5
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "dp_float" 4 (define_insn_reservation "dp_float" 4
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_conv")) (eq_attr "type" "dfp_conv"))
...@@ -445,7 +416,6 @@ ...@@ -445,7 +416,6 @@
;; Group: FE ;; Group: FE
;; Latency: (7,8)/9 ;; Latency: (7,8)/9
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "fp_double_arith" 8 (define_insn_reservation "fp_double_arith" 8
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_arith,dfp_mul")) (eq_attr "type" "dfp_arith,dfp_mul"))
...@@ -455,7 +425,6 @@ ...@@ -455,7 +425,6 @@
;; Group: CO ;; Group: CO
;; Latency: 3/5 ;; Latency: 3/5
;; Issue Rate: 2 ;; Issue Rate: 2
(define_insn_reservation "fp_double_cmp" 3 (define_insn_reservation "fp_double_cmp" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_cmp")) (eq_attr "type" "dfp_cmp"))
...@@ -465,7 +434,6 @@ ...@@ -465,7 +434,6 @@
;; Group: FE ;; Group: FE
;; Latency: (24,25)/26 ;; Latency: (24,25)/26
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "dp_div" 25 (define_insn_reservation "dp_div" 25
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfdiv")) (eq_attr "type" "dfdiv"))
......
gcc/config/sh/sh4a.md
...@@ -19,7 +19,6 @@ ...@@ -19,7 +19,6 @@
;; The following description models the SH4A pipeline ;; The following description models the SH4A pipeline
;; using the DFA based scheduler. ;; using the DFA based scheduler.
(define_automaton "sh4a") (define_automaton "sh4a")
(define_cpu_unit "sh4a_ex" "sh4a") (define_cpu_unit "sh4a_ex" "sh4a")
...@@ -35,7 +34,6 @@ ...@@ -35,7 +34,6 @@
(define_reservation "ID_or" "sh4a_ex|sh4a_ls") (define_reservation "ID_or" "sh4a_ex|sh4a_ls")
(define_reservation "ID_and" "sh4a_ex+sh4a_ls") (define_reservation "ID_and" "sh4a_ex+sh4a_ls")
;; ======================================================= ;; =======================================================
;; Locking Descriptions ;; Locking Descriptions
......
gcc/config/sh/superh.h
...@@ -29,7 +29,6 @@ along with GCC; see the file COPYING3. If not see ...@@ -29,7 +29,6 @@ along with GCC; see the file COPYING3. If not see
This file is intended to override sh.h. */ This file is intended to override sh.h. */
#ifndef _SUPERH_H #ifndef _SUPERH_H
#define _SUPERH_H #define _SUPERH_H
#endif #endif
...@@ -55,7 +54,8 @@ along with GCC; see the file COPYING3. If not see ...@@ -55,7 +54,8 @@ along with GCC; see the file COPYING3. If not see
#endif #endif
/* This is used by the link spec if the boardspecs file is not used (for whatever reason). /* This is used by the link spec if the boardspecs file is not used
(for whatever reason).
If the boardspecs file overrides this then an alternative can be used. */ If the boardspecs file overrides this then an alternative can be used. */
#undef SUBTARGET_EXTRA_SPECS #undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \ #define SUBTARGET_EXTRA_SPECS \
......
gcc/config/sh/ushmedia.h
...@@ -1010,7 +1010,8 @@ sh_media_FMTRXSUB_S (const void *mtrxg, const void *mtrxh, void *mtrxf) ...@@ -1010,7 +1010,8 @@ sh_media_FMTRXSUB_S (const void *mtrxg, const void *mtrxh, void *mtrxf)
__inline__ static __inline__ static
void void
sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi, void *fvf) sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi,
void *fvf)
{ {
sh_media_FTRV_S (mtrxg, fvh, fvf); sh_media_FTRV_S (mtrxg, fvh, fvf);
sh_media_FVADD_S (fvf, fvi, fvf); sh_media_FVADD_S (fvf, fvi, fvf);
...@@ -1018,7 +1019,8 @@ sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi, void *f ...@@ -1018,7 +1019,8 @@ sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi, void *f
__inline__ static __inline__ static
void void
sh_media_FTRVSUB_S (const void *mtrxg, const void *fvh, const void *fvi, void *fvf) sh_media_FTRVSUB_S (const void *mtrxg, const void *fvh, const void *fvi,
void *fvf)
{ {
sh_media_FTRV_S (mtrxg, fvh, fvf); sh_media_FTRV_S (mtrxg, fvh, fvf);
sh_media_FVSUB_S (fvf, fvi, fvf); sh_media_FVSUB_S (fvf, fvi, fvf);
...@@ -1045,7 +1047,8 @@ sh_media_FMTRXMUL_S (const void *mtrxg, const void *mtrxh, void *mtrxf) ...@@ -1045,7 +1047,8 @@ sh_media_FMTRXMUL_S (const void *mtrxg, const void *mtrxh, void *mtrxf)
__inline__ static __inline__ static
void void
sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh, const void *mtrxi, void *mtrxf) sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh,
const void *mtrxi, void *mtrxf)
{ {
const __GCC_FV *g = mtrxg, *i = mtrxi; const __GCC_FV *g = mtrxg, *i = mtrxi;
__GCC_FV *f = mtrxf; __GCC_FV *f = mtrxf;
...@@ -1064,7 +1067,8 @@ sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh, const void *mtrxi, ...@@ -1064,7 +1067,8 @@ sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh, const void *mtrxi,
__inline__ static __inline__ static
void void
sh_media_FMTRXMULSUB_S (const void *mtrxg, const void *mtrxh, const void *mtrxi, void *mtrxf) sh_media_FMTRXMULSUB_S (const void *mtrxg, const void *mtrxh,
const void *mtrxi, void *mtrxf)
{ {
const __GCC_FV *g = mtrxg, *i = mtrxi; const __GCC_FV *g = mtrxg, *i = mtrxi;
__GCC_FV *f = mtrxf; __GCC_FV *f = mtrxf;
......
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