Skip to content

R
riscv-gcc-1
Commit 50fe8924 by Oleg Endo
Options

divtab.c: Fix formatting and comments throughout the file. 

	* config/sh/divtab.c: Fix formatting and comments throughout the file.
	* config/sh/sh4-300.md: Likewise.
	* config/sh/sh4a.md: Likewise.
	* config/sh/constraints.md: Likewise.
	* config/sh/sh.md: Likewise.
	* config/sh/netbsd-elf.h: Likewise.
	* config/sh/predicates.md: Likewise.
	* config/sh/sh-protos.h: Likewise.
	* config/sh/ushmedia.h: Likewise.
	* config/sh/linux.h: Likewise.
	* config/sh/sh.c: Likewise.
	* config/sh/superh.h: Likewise.
	* config/sh/elf.h: Likewise.
	* config/sh/sh4.md: Likewise.
	* config/sh/sh.h: Likewise.

From-SVN: r195703
parent 1a04ac2b
Showing with 51 additions and 68 deletions
gcc/ChangeLog
2013-02-03 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/divtab.c: Fix formatting and comments throughout the file.
* config/sh/sh4-300.md: Likewise.
* config/sh/sh4a.md: Likewise.
* config/sh/constraints.md: Likewise.
* config/sh/sh.md: Likewise.
* config/sh/netbsd-elf.h: Likewise.
* config/sh/predicates.md: Likewise.
* config/sh/sh-protos.h: Likewise.
* config/sh/ushmedia.h: Likewise.
* config/sh/linux.h: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/superh.h: Likewise.
* config/sh/elf.h: Likewise.
* config/sh/sh4.md: Likewise.
* config/sh/sh.h: Likewise.
2013-02-03 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* config/pa/constraints.md: Adjust unused letters. Change "T"
......
gcc/config/sh/constraints.md
......@@ -26,7 +26,7 @@
;; Csu: unsigned 16-bit constant, literal or symbolic
;; Csy: label or symbol
;; Cpg: non-explicit constants that can be directly loaded into a general
;; purpose register in PIC code. like 's' except we don't allow
;; purpose register in PIC code. Like 's' except we don't allow
;; PIC_ADDR_P
;; IJKLMNOP: CONT_INT constants
;; Ixx: signed xx bit
......@@ -315,7 +315,7 @@
(match_test "satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))")))
(define_memory_constraint "Sra"
"A memory reference that uses a simple register addressing."
"A memory reference that uses simple register addressing."
(and (match_test "MEM_P (op)")
(match_test "REG_P (XEXP (op, 0))")))
gcc/config/sh/divtab.c
......@@ -53,7 +53,8 @@ double max_defect3 = 0.;
double max_defect3_x;
int max_defect3_val;
static double note_defect3 (int val, double d2, double y2d, double x)
static double
note_defect3 (int val, double d2, double y2d, double x)
{
int cutoff_val = val >> CUTOFF_BITS;
double cutoff;
......@@ -172,8 +173,10 @@ main ()
printf (" Min defect: %e at %e\n", min_defect, min_defect_x);
printf (" Max 2nd step defect: %e at %e\n", max_defect2, max_defect2_x);
printf (" Min 2nd step defect: %e at %e\n", min_defect2, min_defect2_x);
printf (" Max div defect: %e at %d:%e\n", max_defect3, max_defect3_val, max_defect3_x);
printf (" Min div defect: %e at %d:%e\n", min_defect3, min_defect3_val, min_defect3_x);
printf (" Max div defect: %e at %d:%e\n", max_defect3, max_defect3_val,
max_defect3_x);
printf (" Min div defect: %e at %d:%e\n", min_defect3, min_defect3_val,
min_defect3_x);
printf (" Defect at 1: %e\n",
calc_defect (1., constants[0], factors[0]));
printf (" Defect at -2: %e */\n",
......
gcc/config/sh/elf.h
......@@ -22,17 +22,17 @@ along with GCC; see the file COPYING3. If not see
#undef TARGET_ELF
#define TARGET_ELF 1
/* Generate DWARF2 debugging information and make it the default */
/* Generate DWARF2 debugging information and make it the default. */
#define DWARF2_DEBUGGING_INFO 1
#undef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
/* use a more compact format for line information */
/* Use a more compact format for line information. */
#define DWARF2_ASM_LINE_DEBUG_INFO 1
#undef WCHAR_TYPE
/* #define WCHAR_TYPE (TARGET_SH5 ? "int" : "long int") */
/* #define WCHAR_TYPE (TARGET_SH5 ? "int" : "long int") */
#define WCHAR_TYPE SH_ELF_WCHAR_TYPE
#undef WCHAR_TYPE_SIZE
......@@ -40,7 +40,6 @@ along with GCC; see the file COPYING3. If not see
/* The prefix to add to user-visible assembler symbols. */
#undef LOCAL_LABEL_PREFIX
#define LOCAL_LABEL_PREFIX "."
......
gcc/config/sh/linux.h
......@@ -57,7 +57,6 @@ along with GCC; see the file COPYING3. If not see
%{static:-static}"
/* Output assembler code to STREAM to call the profiler. */
#undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(STREAM,LABELNO) \
do { \
......
gcc/config/sh/netbsd-elf.h
......@@ -41,7 +41,6 @@ along with GCC; see the file COPYING3. If not see
NetBSD ELF LINK_SPEC. */
/* LINK_EMUL_PREFIX from sh/elf.h */
#undef SUBTARGET_LINK_EMUL_SUFFIX
#define SUBTARGET_LINK_EMUL_SUFFIX "_nbsd"
......
gcc/config/sh/sh-protos.h
......@@ -212,7 +212,8 @@ extern void sh_pr_nosave_low_regs (struct cpp_reader *);
extern rtx function_symbol (rtx, const char *, enum sh_function_kind);
extern rtx sh_get_pr_initial_val (void);
extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, signed int, enum machine_mode);
extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree,
signed int, enum machine_mode);
extern rtx sh_dwarf_register_span (rtx);
extern rtx replace_n_hard_rtx (rtx, rtx *, int , int);
......
gcc/config/sh/sh4-300.md
......@@ -35,26 +35,21 @@
;; Since SH4 is a dual issue machine,it is as if there are two
;; units so that any insn can be processed by either one
;; of the decoding unit.
(define_cpu_unit "sh4_300_pipe_01,sh4_300_pipe_02" "sh4_300_inst_pipeline")
;; The floating point units.
(define_cpu_unit "sh4_300_fpt,sh4_300_fpu,sh4_300_fds" "sh4_300_fpu_pipe")
;; integer multiplier unit
(define_cpu_unit "sh4_300_mul" "sh4_300_inst_pipeline")
;; LS unit
(define_cpu_unit "sh4_300_ls" "sh4_300_inst_pipeline")
;; The address calculator used for branch instructions.
;; This will be reserved after "issue" of branch instructions
;; and this is to make sure that no two branch instructions
;; can be issued in parallel.
(define_cpu_unit "sh4_300_br" "sh4_300_inst_pipeline")
;; ----------------------------------------------------
......@@ -85,7 +80,6 @@
"sh4_300_issue+sh4_300_mul")
;; Instructions without specific resource requirements with latency 1.
(define_insn_reservation "sh4_300_simple_arith" 1
(and (eq_attr "pipe_model" "sh4_300")
(eq_attr "type" "mt_group,arith,dyn_shift,prset"))
......@@ -153,7 +147,6 @@
;; or likely and likely not predicted, we might want to fill the delay slot.
;; However, there appears to be no machinery to make the compiler
;; recognize these scenarios.
(define_insn_reservation "sh4_300_branch" 1
(and (eq_attr "pipe_model" "sh4_300")
(eq_attr "type" "cbranch,jump,return,jump_ind"))
......@@ -169,8 +162,11 @@
;; Group: CO
;; Latency: 1-5
;; Issue Rate: 1
;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
;; cwb is used for the sequence
;; ocbwb @%0
;; extu.w %0,%2
;; or %1,%2
;; mov.l %0,@%2
;; This description is likely inexact, but this pattern should not actually
;; appear when compiling for sh4-300; we should use isbi instead.
;; If a -mtune option is added later, we should use the icache array
......@@ -197,7 +193,6 @@
;; since there are no instructions that contend for memory access early.
;; We could, of course, provide exact scheduling information for specific
;; sfuncs, if that should prove useful.
(define_insn_reservation "sh4_300_call" 16
(and (eq_attr "pipe_model" "sh4_300")
(eq_attr "type" "call,sfunc"))
......@@ -265,7 +260,6 @@
(eq_attr "type" "dfdiv"))
"sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*31")
;; ??? We don't really want these for sh4-300.
;; this pattern itself is likely to finish in 3 cycles, but also
;; to disrupt branch prediction for taken branches for the following
......
gcc/config/sh/sh4.md
......@@ -41,35 +41,29 @@
;; Two automata are defined to reduce number of states
;; which a single large automaton will have. (Factoring)
(define_automaton "inst_pipeline,fpu_pipe")
;; This unit is basically the decode unit of the processor.
;; Since SH4 is a dual issue machine,it is as if there are two
;; units so that any insn can be processed by either one
;; of the decoding unit.
(define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
;; The fixed point arithmetic calculator(?? EX Unit).
(define_cpu_unit "int" "inst_pipeline")
;; f1_1 and f1_2 are floating point units.Actually there is
;; a f1 unit which can overlap with other f1 unit but
;; not another F1 unit.It is as though there were two
;; f1 units.
(define_cpu_unit "f1_1,f1_2" "fpu_pipe")
;; The floating point units (except FS - F2 always precedes it.)
(define_cpu_unit "F0,F1,F2,F3" "fpu_pipe")
;; This is basically the MA unit of SH4
;; used in LOAD/STORE pipeline.
(define_cpu_unit "memory" "inst_pipeline")
;; However, there are LS group insns that don't use it, even ones that
......@@ -85,12 +79,10 @@
;; ----------------------------------------------------
;; This reservation is to simplify the dual issue description.
(define_reservation "issue" "pipe_01|pipe_02")
;; This is to express the locking of D stage.
;; Note that the issue of a CO group insn also effectively locks the D stage.
(define_reservation "d_lock" "pipe_01+pipe_02")
;; Every FE instruction but fipr / ftrv starts with issue and this.
......@@ -98,12 +90,10 @@
;; This is to simplify description where F1,F2,FS
;; are used simultaneously.
(define_reservation "fpu" "F1+F2")
;; This is to highlight the fact that f1
;; cannot overlap with F1.
(exclusion_set "f1_1,f1_2" "F1")
(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
......@@ -113,14 +103,12 @@
;; for one cycle.
;; Group: MT
(define_insn_reservation "reg_mov" 0
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "move"))
"issue")
;; Group: LS
(define_insn_reservation "freg_mov" 0
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fmove"))
......@@ -145,7 +133,6 @@
;; Group: MT
;; Latency: 1
;; Issue Rate: 1
(define_insn_reservation "mt" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mt_group"))
......@@ -155,7 +142,6 @@
;; Group: EX
;; Latency: 1
;; Issue Rate: 1
(define_insn_reservation "sh4_simple_arith" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "insn_class" "ex_group"))
......@@ -178,7 +164,6 @@
;; Group: LS
;; Latency: 2
;; Issue Rate: 1
(define_insn_reservation "sh4_load" 2
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "load,pcload"))
......@@ -220,7 +205,6 @@
;; Group: LS
;; Latency: 1
;; Issue Rate: 1
(define_insn_reservation "sh4_gp_fpul" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "gp_fpul"))
......@@ -230,7 +214,6 @@
;; Group: LS
;; Latency: 3
;; Issue Rate: 1
(define_insn_reservation "sh4_fpul_gp" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fpul_gp"))
......@@ -246,7 +229,6 @@
;; ??? If the branch is likely, we might want to fill the delay slot;
;; if the branch is likely, but not very likely, should we pretend to use
;; a resource that CO instructions use, to get a pairable delay slot insn?
(define_insn_reservation "sh4_branch" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "cbranch,jump"))
......@@ -258,7 +240,6 @@
;; Issue Rate: 2
;; ??? Scheduling happens before branch shortening, and hence jmp and braf
;; can't be distinguished from bra for the "jump" pattern.
(define_insn_reservation "sh4_return" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "return,jump_ind"))
......@@ -270,7 +251,6 @@
;; Issue Rate: 5
;; this instruction can be executed in any of the pipelines
;; and blocks the pipeline for next 4 stages.
(define_insn_reservation "sh4_return_from_exp" 5
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "rte"))
......@@ -280,8 +260,11 @@
;; Group: CO
;; Latency: 1-5
;; Issue Rate: 1
;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
;; cwb is used for the sequence
;; ocbwb @%0
;; extu.w %0,%2
;; or %1,%2
;; mov.l %0,@%2
;; ocbwb on its own would be "d_lock,nothing,memory*5"
(define_insn_reservation "ocbwb" 6
(and (eq_attr "pipe_model" "sh4")
......@@ -298,7 +281,6 @@
;; or when we are doing a function call - and we don't do inter-function
;; scheduling. For the function call case, it's really best that we end with
;; something that models an rts.
(define_insn_reservation "sh4_lds_to_pr" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "prset") )
......@@ -311,7 +293,6 @@
;; since there are no instructions that contend for memory access early.
;; We could, of course, provide exact scheduling information for specific
;; sfuncs, if that should prove useful.
(define_insn_reservation "sh4_call" 16
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "call,sfunc"))
......@@ -322,7 +303,6 @@
;; Latency: 3
;; Issue Rate: 2
;; The SX unit is blocked for last 2 cycles.
(define_insn_reservation "ldsmem_to_pr" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "pload"))
......@@ -333,7 +313,6 @@
;; Latency: 2
;; Issue Rate: 2
;; The SX unit in second and third cycles.
(define_insn_reservation "sts_from_pr" 2
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "prget"))
......@@ -343,7 +322,6 @@
;; Group: CO
;; Latency: 2
;; Issue Rate: 2
(define_insn_reservation "sh4_prstore_mem" 2
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "pstore"))
......@@ -354,7 +332,6 @@
;; Latency: 4
;; Issue Rate: 1
;; F1 is blocked for last three cycles.
(define_insn_reservation "fpscr_load" 4
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "gp_fpscr"))
......@@ -366,7 +343,6 @@
;; Latency to update Rn is 1 and latency to update FPSCR is 4
;; Issue Rate: 1
;; F1 is blocked for last three cycles.
(define_insn_reservation "fpscr_load_mem" 4
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mem_fpscr"))
......@@ -377,7 +353,6 @@
;; Group: CO
;; Latency: 4 / 4
;; Issue Rate: 2
(define_insn_reservation "multi" 4
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "smpy,dmpy"))
......@@ -387,7 +362,6 @@
;; Group: CO
;; Latency: 3
;; Issue Rate: 1
(define_insn_reservation "sh4_mac_gp" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mac_gp,gp_mac,mem_mac"))
......@@ -399,7 +373,6 @@
;; Group: FE
;; Latency: 3/4
;; Issue Rate: 1
(define_insn_reservation "fp_arith" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fp,fp_cmp"))
......@@ -424,7 +397,6 @@
;; Latency: 12/13 (FDIV); 11/12 (FSQRT)
;; Issue Rate: 1
;; We describe fdiv here; fsqrt is actually one cycle faster.
(define_insn_reservation "fp_div" 12
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fdiv"))
......@@ -435,7 +407,6 @@
;; Group: FE
;; Latency: (3,4)/5
;; Issue Rate: 1
(define_insn_reservation "dp_float" 4
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_conv"))
......@@ -445,7 +416,6 @@
;; Group: FE
;; Latency: (7,8)/9
;; Issue Rate: 1
(define_insn_reservation "fp_double_arith" 8
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_arith,dfp_mul"))
......@@ -455,7 +425,6 @@
;; Group: CO
;; Latency: 3/5
;; Issue Rate: 2
(define_insn_reservation "fp_double_cmp" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_cmp"))
......@@ -465,7 +434,6 @@
;; Group: FE
;; Latency: (24,25)/26
;; Issue Rate: 1
(define_insn_reservation "dp_div" 25
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfdiv"))
......
gcc/config/sh/sh4a.md
......@@ -19,7 +19,6 @@
;; The following description models the SH4A pipeline
;; using the DFA based scheduler.
(define_automaton "sh4a")
(define_cpu_unit "sh4a_ex" "sh4a")
......@@ -35,7 +34,6 @@
(define_reservation "ID_or" "sh4a_ex|sh4a_ls")
(define_reservation "ID_and" "sh4a_ex+sh4a_ls")
;; =======================================================
;; Locking Descriptions
......
gcc/config/sh/superh.h
......@@ -29,7 +29,6 @@ along with GCC; see the file COPYING3. If not see
This file is intended to override sh.h. */
#ifndef _SUPERH_H
#define _SUPERH_H
#endif
......@@ -55,7 +54,8 @@ along with GCC; see the file COPYING3. If not see
#endif
/* This is used by the link spec if the boardspecs file is not used (for whatever reason).
/* This is used by the link spec if the boardspecs file is not used
(for whatever reason).
If the boardspecs file overrides this then an alternative can be used. */
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
......
gcc/config/sh/ushmedia.h
......@@ -1010,7 +1010,8 @@ sh_media_FMTRXSUB_S (const void *mtrxg, const void *mtrxh, void *mtrxf)
__inline__ static
void
sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi, void *fvf)
sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi,
void *fvf)
{
sh_media_FTRV_S (mtrxg, fvh, fvf);
sh_media_FVADD_S (fvf, fvi, fvf);
......@@ -1018,7 +1019,8 @@ sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi, void *f
__inline__ static
void
sh_media_FTRVSUB_S (const void *mtrxg, const void *fvh, const void *fvi, void *fvf)
sh_media_FTRVSUB_S (const void *mtrxg, const void *fvh, const void *fvi,
void *fvf)
{
sh_media_FTRV_S (mtrxg, fvh, fvf);
sh_media_FVSUB_S (fvf, fvi, fvf);
......@@ -1045,7 +1047,8 @@ sh_media_FMTRXMUL_S (const void *mtrxg, const void *mtrxh, void *mtrxf)
__inline__ static
void
sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh, const void *mtrxi, void *mtrxf)
sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh,
const void *mtrxi, void *mtrxf)
{
const __GCC_FV *g = mtrxg, *i = mtrxi;
__GCC_FV *f = mtrxf;
......@@ -1064,7 +1067,8 @@ sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh, const void *mtrxi,
__inline__ static
void
sh_media_FMTRXMULSUB_S (const void *mtrxg, const void *mtrxh, const void *mtrxi, void *mtrxf)
sh_media_FMTRXMULSUB_S (const void *mtrxg, const void *mtrxh,
const void *mtrxi, void *mtrxf)
{
const __GCC_FV *g = mtrxg, *i = mtrxi;
__GCC_FV *f = mtrxf;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment