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riscv-gcc-1
Commit 50d38551 by Ian Bolton Committed by Ian Bolton
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AArch64 - allow insv_imm to handle bigger immediates via masking to 16 bits 

From-SVN: r199293
parent f746a029
Showing with 11 additions and 5 deletions
gcc/ChangeLog
2013-05-24 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.c (aarch64_print_operand): Change the
X format specifier to only display bottom 16 bits.
* config/aarch64/aarch64.md (insv_imm<mode>): Allow any size of
immediate to match for operand 2, since it will be masked.
2013-05-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/57287
......
gcc/config/aarch64/aarch64.c
......@@ -3428,13 +3428,13 @@ aarch64_print_operand (FILE *f, rtx x, char code)
break;
case 'X':
/* Print integer constant in hex. */
/* Print bottom 16 bits of integer constant in hex. */
if (GET_CODE (x) != CONST_INT)
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
asm_fprintf (f, "0x%wx", UINTVAL (x));
asm_fprintf (f, "0x%wx", UINTVAL (x) & 0xffff);
break;
case 'w':
......
gcc/config/aarch64/aarch64.md
......@@ -858,9 +858,8 @@
(const_int 16)
(match_operand:GPI 1 "const_int_operand" "n"))
(match_operand:GPI 2 "const_int_operand" "n"))]
"INTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)
&& INTVAL (operands[1]) % 16 == 0
&& UINTVAL (operands[2]) <= 0xffff"
"UINTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)
&& UINTVAL (operands[1]) % 16 == 0"
"movk\\t%<w>0, %X2, lsl %1"
[(set_attr "v8type" "movk")
(set_attr "mode" "<MODE>")]
......
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