MIPS SB-1 DFA scheduler.

* config/mips/mips-protos.h (fp_register_operand, lo_operand): Declare.
* config/mips/mips.c (mips_multipass_dfa_lookahead): Declare.
(TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): New.
(fp_register_operand, lo_operand): New.
(mips_rtx_costs): Add TUNE_SB1 support.
(mips_issue_rate): Add comment.  Add PROCESSOR_SB1 support.
(mips_use_dfa_pipeline_interface): Add PROCESSOR_SB1 support.
(mips_multipass_dfa_lookahead): New.
* config/mips/mips.h (MASK_FP_EXCEPTIONS, TARGET_FP_EXCEPTIONS,
TUNE_SB1): New.
(TARGET_SWITCHES): Add -mfp-exceptions support.
(TARGET_FP_EXCEPTIONS_DEFAULT): New.
(BRANCH_COST): Fix whitespace.
* config/mips/mips.md: Include sb1.md.
* config/mips/sb1.md: New file.
* doc/invoke.texi: Document -mfp-exceptions.

From-SVN: r80988

gcc/ChangeLog

@@ -10,6 +10,23 @@
 
 2004-04-21  James E Wilson  <wilson@specifixinc.com>
 
+	* config/mips/mips-protos.h (fp_register_operand, lo_operand): Declare.
+	* config/mips/mips.c (mips_multipass_dfa_lookahead): Declare.
+	(TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): New.
+	(fp_register_operand, lo_operand): New.
+	(mips_rtx_costs): Add TUNE_SB1 support.
+	(mips_issue_rate): Add comment.  Add PROCESSOR_SB1 support.
+	(mips_use_dfa_pipeline_interface): Add PROCESSOR_SB1 support.
+	(mips_multipass_dfa_lookahead): New.
+	* config/mips/mips.h (MASK_FP_EXCEPTIONS, TARGET_FP_EXCEPTIONS,
+	TUNE_SB1): New.
+	(TARGET_SWITCHES): Add -mfp-exceptions support.
+	(TARGET_FP_EXCEPTIONS_DEFAULT): New.
+	(BRANCH_COST): Fix whitespace.
+	* config/mips/mips.md: Include sb1.md.
+	* config/mips/sb1.md: New file.
+	* doc/invoke.texi: Document -mfp-exceptions.
+
 	* Makefile.in (fixinc.sh): Don't set or export WARN_CFLAGS.  Fix
 	comment.
 	* fixinc/Makefile.in (FL_LIST): Don't mention WARN_CFLAGS.

gcc/config/mips/mips-protos.h

@@ -93,6 +93,8 @@ extern int mips_address_insns (rtx, enum machine_mode);
 extern int mips_const_insns (rtx);
 extern int mips_fetch_insns (rtx);
 extern int mips_idiv_insns (void);
+extern int fp_register_operand (rtx, enum machine_mode);
+extern int lo_operand (rtx, enum machine_mode);
 extern bool mips_legitimate_address_p (enum machine_mode, rtx, int);
 extern rtx mips_unspec_address (rtx, enum mips_symbol_type);
 extern bool mips_legitimize_address (rtx *, enum machine_mode);

gcc/config/mips/mips.c

@@ -232,6 +232,7 @@ static bool mips_return_in_memory (tree, tree);
 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
 static int mips_issue_rate (void);
 static int mips_use_dfa_pipeline_interface (void);
+static int mips_multipass_dfa_lookahead (void);
 static void mips_init_libfuncs (void);
 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
 					 tree, int *, int);
@@ -680,6 +681,9 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
+#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
+#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
+  mips_multipass_dfa_lookahead
 
 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
@@ -1661,6 +1665,23 @@ stack_operand (rtx op, enum machine_mode mode)
 	  && addr.reg == stack_pointer_rtx);
 }
 
+/* Helper function for DFA schedulers.  Return true if OP is a floating
+   point register.  */
+
+int
+fp_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return REG_P (op) && FP_REG_P (REGNO (op));
+}
+
+/* Helper function for DFA schedulers.  Return true if OP is a LO reg.  */
+
+int
+lo_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return REG_P (op) && REGNO (op) == LO_REGNUM;
+}
+
 
 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS.  It
    returns a nonzero value if X is a legitimate address for a memory
@@ -2265,6 +2286,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
             *total = COSTS_N_INSNS (2);
           else if (TUNE_MIPS6000)
             *total = COSTS_N_INSNS (3);
+	  else if (TUNE_SB1)
+	    *total = COSTS_N_INSNS (4);
           else
             *total = COSTS_N_INSNS (6);
           return true;
@@ -2289,7 +2312,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
         {
           if (TUNE_MIPS3000
               || TUNE_MIPS3900
-              || TUNE_MIPS5000)
+              || TUNE_MIPS5000
+	      || TUNE_SB1)
             *total = COSTS_N_INSNS (4);
           else if (TUNE_MIPS6000
                    || TUNE_MIPS5400
@@ -2302,7 +2326,9 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
 
       if (mode == DFmode)
         {
-          if (TUNE_MIPS3000
+          if (TUNE_SB1)
+	    *total = COSTS_N_INSNS (4);
+          else if (TUNE_MIPS3000
               || TUNE_MIPS3900
               || TUNE_MIPS5000)
             *total = COSTS_N_INSNS (5);
@@ -2319,7 +2345,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
         *total = COSTS_N_INSNS (12);
       else if (TUNE_MIPS3900)
         *total = COSTS_N_INSNS (2);
-      else if (TUNE_MIPS5400 || TUNE_MIPS5500)
+      else if (TUNE_MIPS5400 || TUNE_MIPS5500 || TUNE_SB1)
         *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
       else if (TUNE_MIPS7000)
         *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
@@ -2342,6 +2368,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
             *total = COSTS_N_INSNS (12);
           else if (TUNE_MIPS6000)
             *total = COSTS_N_INSNS (15);
+	  else if (TUNE_SB1)
+	    *total = COSTS_N_INSNS (24);
           else if (TUNE_MIPS5400 || TUNE_MIPS5500)
             *total = COSTS_N_INSNS (30);
           else
@@ -2358,6 +2386,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
             *total = COSTS_N_INSNS (59);
           else if (TUNE_MIPS6000)
             *total = COSTS_N_INSNS (16);
+	  else if (TUNE_SB1)
+	    *total = COSTS_N_INSNS (32);
           else
             *total = COSTS_N_INSNS (36);
           return true;
@@ -2373,6 +2403,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
         *total = COSTS_N_INSNS (38);
       else if (TUNE_MIPS5000)
         *total = COSTS_N_INSNS (36);
+      else if (TUNE_SB1)
+	*total = COSTS_N_INSNS ((mode == SImode) ? 36 : 68);
       else if (TUNE_MIPS5400 || TUNE_MIPS5500)
         *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
       else
@@ -9292,6 +9324,8 @@ mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
 {
   return !TARGET_OLDABI;
 }
+
+/* Return the number of instructions that can be issued per cycle.  */
 
 static int
 mips_issue_rate (void)
@@ -9304,6 +9338,13 @@ mips_issue_rate (void)
     case PROCESSOR_R9000:
       return 2;
 
+    case PROCESSOR_SB1:
+      /* This is actually 4, but we get better performance if we claim 3.
+	 This is partly because of unwanted speculative code motion with the
+	 larger number, and partly because in most common cases we can't
+	 reach the theoretical max of 4.  */
+      return 3;
+
     default:
       return 1;
     }
@@ -9324,6 +9365,7 @@ mips_use_dfa_pipeline_interface (void)
     case PROCESSOR_R5500:
     case PROCESSOR_R7000:
     case PROCESSOR_R9000:
+    case PROCESSOR_SB1:
     case PROCESSOR_SR71000:
       return true;
 
@@ -9332,6 +9374,19 @@ mips_use_dfa_pipeline_interface (void)
     }
 }
 
+/* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD.  This should
+   be as wide as the scheduling freedom in the DFA.  */
+
+static int
+mips_multipass_dfa_lookahead (void)
+{
+  /* Can schedule up to 4 of the 6 function units in any one cycle.  */
+  if (mips_tune == PROCESSOR_SB1)
+    return 4;
+
+  return 0;
+}
+
 
 const char *
 mips_emit_prefetch (rtx *operands)

gcc/config/mips/mips.h

@@ -173,6 +173,8 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define MASK_FIX_SB1	   0x04000000	/* Work around SB-1 errata.  */
 #define MASK_FIX_VR4120	   0x08000000   /* Work around VR4120 errata.  */
 
+#define MASK_FP_EXCEPTIONS 0x10000000   /* FP exceptions are enabled.  */
+
 					/* Debug switches, not documented */
 #define MASK_DEBUG	0		/* unused */
 #define MASK_DEBUG_C	0		/* don't expand seq, etc.  */
@@ -257,6 +259,8 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define TARGET_FIX_R4400	(target_flags & MASK_FIX_R4400)
 #define TARGET_FIX_VR4120	(target_flags & MASK_FIX_VR4120)
 
+#define TARGET_FP_EXCEPTIONS	(target_flags & MASK_FP_EXCEPTIONS)
+
 /* True if we should use NewABI-style relocation operators for
    symbolic addresses.  This is never true for mips16 code,
    which has its own conventions.  */
@@ -339,6 +343,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define TUNE_MIPS6000               (mips_tune == PROCESSOR_R6000)
 #define TUNE_MIPS7000               (mips_tune == PROCESSOR_R7000)
 #define TUNE_MIPS9000               (mips_tune == PROCESSOR_R9000)
+#define TUNE_SB1                    (mips_tune == PROCESSOR_SB1)
 
 #define TARGET_OLDABI		    (mips_abi == ABI_32 || mips_abi == ABI_O64)
 #define TARGET_NEWABI		    (mips_abi == ABI_N32 || mips_abi == ABI_64)
@@ -630,6 +635,10 @@ extern const struct mips_cpu_info *mips_tune_info;
      N_("Lift restrictions on GOT size") },				\
   {"no-xgot",		 -MASK_XGOT,					\
      N_("Do not lift restrictions on GOT size") },			\
+  {"fp-exceptions",	  MASK_FP_EXCEPTIONS,				\
+     N_("FP exceptions are enabled") },					\
+  {"no-fp-exceptions", 	  -MASK_FP_EXCEPTIONS,				\
+     N_("FP exceptions are not enabled") },				\
   {"debug",		  MASK_DEBUG,					\
      NULL},								\
   {"debugc",		  MASK_DEBUG_C,					\
@@ -640,7 +649,8 @@ extern const struct mips_cpu_info *mips_tune_info;
      NULL},								\
   {"",			  (TARGET_DEFAULT				\
 			   | TARGET_CPU_DEFAULT				\
-			   | TARGET_ENDIAN_DEFAULT),			\
+			   | TARGET_ENDIAN_DEFAULT			\
+			   | TARGET_FP_EXCEPTIONS_DEFAULT),		\
      NULL},								\
 }
 
@@ -658,6 +668,10 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
 #endif
 
+#ifndef TARGET_FP_EXCEPTIONS_DEFAULT
+#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
+#endif
+
 /* 'from-abi' makes a good default: you get whatever the ABI requires.  */
 #ifndef MIPS_ISA_DEFAULT
 #ifndef MIPS_CPU_STRING_DEFAULT
@@ -2674,7 +2688,7 @@ typedef struct mips_args {
 /* ??? Fix this to be right for the R8000.  */
 #define BRANCH_COST							\
   ((! TARGET_MIPS16							\
-    && (TUNE_MIPS4000 || TUNE_MIPS6000))	\
+    && (TUNE_MIPS4000 || TUNE_MIPS6000))				\
    ? 2 : 1)
 
 /* If defined, modifies the length assigned to instruction INSN as a

gcc/config/mips/mips.md

@@ -628,6 +628,7 @@
 (include "5500.md")
 (include "7000.md")
 (include "9000.md")
+(include "sb1.md")
 (include "sr71k.md")
 
 ;;

gcc/doc/invoke.texi

@@ -482,7 +482,8 @@ in the following sections.
 -mfix-r4000  -mno-fix-r4000  -mfix-r4400  -mno-fix-r4400 @gol
 -mfix-vr4120  -mno-fix-vr4120  -mfix-sb1  -mno-fix-sb1 @gol
 -mflush-func=@var{func}  -mno-flush-func @gol
--mbranch-likely  -mno-branch-likely}
+-mbranch-likely  -mno-branch-likely @gol
+-mfp-exceptions -mno-fp-exceptions}
 
 @emph{i386 and x86-64 Options}
 @gccoptlist{-mtune=@var{cpu-type}  -march=@var{cpu-type} @gol
@@ -8178,6 +8179,17 @@ architecture.  An exception is for the MIPS32 and MIPS64 architectures
 and processors which implement those architectures; for those, Branch
 Likely instructions will not be generated by default because the MIPS32
 and MIPS64 architectures specifically deprecate their use.
+
+@item -mfp-exceptions
+@itemx -mno-fp-exceptions
+@opindex mfp-exceptions
+Specifies whether FP exceptions are enabled.  This affects how we schedule
+FP instructions for some processors.  The default is that FP exceptions are
+enabled.
+
+For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
+64-bit code, then we can use both FP pipes.  Otherwise, we can only use one
+FP pipe.
 @end table
 
 @node i386 and x86-64 Options