mips.c (build_mips16_call_stub): On 64-bit targets, combine an SC return value…

mips.c (build_mips16_call_stub): On 64-bit targets, combine an SC return value into a single register.

gcc/
	* config/mips/mips.c (build_mips16_call_stub): On 64-bit targets,
	combine an SC return value into a single register.

From-SVN: r128700

gcc/ChangeLog

 2007-09-23  Richard Sandiford  <rsandifo@nildram.co.uk>
 
+	* config/mips/mips.c (build_mips16_call_stub): On 64-bit targets,
+	combine an SC return value into a single register.
+
+2007-09-23  Richard Sandiford  <rsandifo@nildram.co.uk>
+
 	* opth-gen.awk (target_flags_explicit): Declare.
 	* toplev.h (target_flags_explicit): Delete declaration.
 	* toplev.c (target_flags): Likewise.

gcc/config/mips/mips.c

@@ -10055,6 +10055,19 @@ build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
 	      fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
 		       reg_names[GP_REG_FIRST + 2],
 		       reg_names[FP_REG_FIRST + 0]);
+	      if (GET_MODE (retval) == SCmode && TARGET_64BIT)
+		{
+		  /* On 64-bit targets, complex floats are returned in
+		     a single GPR, such that "sd" on a suitably-aligned
+		     target would store the value correctly.  */
+		  fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
+			   reg_names[GP_REG_FIRST + 2 + TARGET_LITTLE_ENDIAN],
+			   reg_names[GP_REG_FIRST + 2 + TARGET_LITTLE_ENDIAN]);
+		  fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
+			   reg_names[GP_REG_FIRST + 2],
+			   reg_names[GP_REG_FIRST + 2],
+			   reg_names[GP_REG_FIRST + 3]);
+		}
 	      break;
 
 	    case DCmode: