re PR rtl-optimization/54472 (ICE (spill_failure): unable to find a register to…

re PR rtl-optimization/54472 (ICE (spill_failure): unable to find a register to spill in class 'AREG' with -O -fschedule-insns -fselective-scheduling)

	PR rtl-optimization/54472

	* sel-sched-ir.c (has_dependence_note_reg_set): Handle implicit sets.
	(has_dependence_note_reg_clobber,
	has_dependence_note_reg_use): Likewise.
    
	* gcc.dg/pr54472.c: New test.

From-SVN: r193358

gcc/ChangeLog

+2012-11-09  Andrey Belevantsev  <abel@ispras.ru>
+
+	PR rtl-optimization/54472
+
+	* sel-sched-ir.c (has_dependence_note_reg_set): Handle implicit sets.
+	(has_dependence_note_reg_clobber,
+	has_dependence_note_reg_use): Likewise. 
+
 2012-11-09  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* config/i386/i386.c (release_scratch_register_on_entry): Also adjust

gcc/sel-sched-ir.c

@@ -3185,7 +3185,7 @@ has_dependence_note_reg_set (int regno)
 	  || reg_last->clobbers != NULL)
 	*dsp = (*dsp & ~SPECULATIVE) | DEP_OUTPUT;
 
-      if (reg_last->uses)
+      if (reg_last->uses || reg_last->implicit_sets)
 	*dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI;
     }
 }
@@ -3205,7 +3205,7 @@ has_dependence_note_reg_clobber (int regno)
       if (reg_last->sets)
 	*dsp = (*dsp & ~SPECULATIVE) | DEP_OUTPUT;
 
-      if (reg_last->uses)
+      if (reg_last->uses || reg_last->implicit_sets)
 	*dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI;
     }
 }
@@ -3225,7 +3225,7 @@ has_dependence_note_reg_use (int regno)
       if (reg_last->sets)
 	*dsp = (*dsp & ~SPECULATIVE) | DEP_TRUE;
 
-      if (reg_last->clobbers)
+      if (reg_last->clobbers || reg_last->implicit_sets)
 	*dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI;
 
       /* Merge BE_IN_SPEC bits into *DSP when the dependency producer

gcc/testsuite/ChangeLog

+2012-11-09  Andrey Belevantsev  <abel@ispras.ru>
+
+	PR rtl-optimization/54472
+	
+	* gcc.dg/pr54472.c: New test. 
+
 2012-11-09  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gnat.dg/stack_check3.ad[sb]: New test.

gcc/testsuite/gcc.dg/pr54472.c

+/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-options "-O -fschedule-insns -fselective-scheduling" } */
+
+int main ()
+{
+  int a[3][3][3];
+  __builtin_memset (a, 0, sizeof a);
+  return 0;
+}