[AArch64] Tweak sve/vcond_6.c test

sve/vcond_6.c was effectively testing a three-input logical operation,
since the result of BINOP needed to be ANDed with the loop predicate
before loading src[i].  This patch makes it really test a binary
operation instead.  A later patch will add (and optimise) the
three-operand case.

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
	* gcc.target/aarch64/sve/vcond_6.c (LOOP): Unconditionally
	load from src[i].

From-SVN: r260028

gcc/testsuite/ChangeLog

+2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.target/aarch64/sve/vcond_6.c (LOOP): Unconditionally
+	load from src[i].
+
 2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	PR c++/80691

gcc/testsuite/gcc.target/aarch64/sve/vcond_6.c

@@ -19,9 +19,12 @@
 			 TYPE fallback, int count)			\
   {									\
     for (int i = 0; i < count; ++i)					\
-      dest[i] = (BINOP (__builtin_isunordered (a[i], b[i]),		\
-			__builtin_isunordered (c[i], d[i]))		\
-		 ? src[i] : fallback);					\
+      {									\
+	TYPE srcv = src[i];						\
+	dest[i] = (BINOP (__builtin_isunordered (a[i], b[i]),		\
+			  __builtin_isunordered (c[i], d[i]))		\
+		   ? srcv : fallback);					\
+      }									\
   }
 
 #define TEST_BINOP(T, BINOP) \
@@ -40,9 +43,7 @@
 
 TEST_ALL (LOOP)
 
-/* Currently we don't manage to remove ANDs from the other loops.  */
-/* { dg-final { scan-assembler-times {\tand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler {\tand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} } } */
+/* { dg-final { scan-assembler-times {\tand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */
 /* { dg-final { scan-assembler-times {\torr\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */
 /* { dg-final { scan-assembler-times {\teor\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */
 /* { dg-final { scan-assembler-times {\tnand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */