Arm: Fix NEON REG to REG reload failures. (PR/target 88850)

We currently return cost 2 for NEON REG to REG moves, which would be incorrect
for 64 bit moves.  We currently don't have a pattern for this in the neon_move
alternatives because this is a bit of a special case.  We would almost never
want it to use this r -> r pattern unless it really has no choice.

As such we add a new neon r -> r move pattern but also hide it from being used
to determine register preferences and also disparage it during LRA.

gcc/ChangeLog:

	PR/target 88850
	* config/arm/neon.md (*neon_mov<mode>): Add r -> r case.

gcc/testsuite/ChangeLog:

	PR/target 88850
	* gcc.target/arm/pr88850.c: New test.

From-SVN: r268612

gcc/ChangeLog

+2019-02-07  Tamar Christina  <tamar.christina@arm.com>
+
+	PR/target 88850
+	* config/arm/neon.md (*neon_mov<mode>): Add r -> r case.
+
 2019-02-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* config/arm/neon.md (neon_<sup>dot<vsi2qi>):

gcc/config/arm/neon.md

@@ -25,9 +25,9 @@
 
 (define_insn "*neon_mov<mode>"
   [(set (match_operand:VDX 0 "nonimmediate_operand"
-	  "=w,Un,w, w,  ?r,?w,?r, ?Us")
+	  "=w,Un,w, w,  ?r,?w,?r, ?Us,*r")
 	(match_operand:VDX 1 "general_operand"
-	  " w,w, Dn,Uni, w, r, Usi,r"))]
+	  " w,w, Dn,Uni, w, r, Usi,r,*r"))]
   "TARGET_NEON
    && (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[1], <MODE>mode))"
@@ -57,16 +57,17 @@
     case 2: gcc_unreachable ();
     case 4: return "vmov\t%Q0, %R0, %P1  @ <mode>";
     case 5: return "vmov\t%P0, %Q1, %R1  @ <mode>";
+    case 8: return "#";
     default: return output_move_double (operands, true, NULL);
     }
 }
  [(set_attr "type" "neon_move<q>,neon_store1_1reg,neon_move<q>,\
                     neon_load1_1reg, neon_to_gp<q>,neon_from_gp<q>,\
-                    neon_load1_2reg, neon_store1_2reg")
-  (set_attr "length" "4,4,4,4,4,4,8,8")
-  (set_attr "arm_pool_range"     "*,*,*,1020,*,*,1020,*")
-  (set_attr "thumb2_pool_range"     "*,*,*,1018,*,*,1018,*")
-  (set_attr "neg_pool_range" "*,*,*,1004,*,*,1004,*")])
+                    neon_load1_2reg, neon_store1_2reg, multiple")
+  (set_attr "length" "4,4,4,4,4,4,8,8,8")
+  (set_attr "arm_pool_range"     "*,*,*,1020,*,*,1020,*,*")
+  (set_attr "thumb2_pool_range"     "*,*,*,1018,*,*,1018,*,*")
+  (set_attr "neg_pool_range" "*,*,*,1004,*,*,1004,*,*")])
 
 (define_insn "*neon_mov<mode>"
   [(set (match_operand:VQXMOV 0 "nonimmediate_operand"

gcc/testsuite/ChangeLog

+2019-02-07  Tamar Christina  <tamar.christina@arm.com>
+
+	PR/target 88850
+	* gcc.target/arm/pr88850.c: New test.
+
 2019-02-07  Alexandre Oliva <aoliva@redhat.com>
 
 	PR c++/86218

gcc/testsuite/gcc.target/arm/pr88850.c

+/* PR target/88850 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon -fdump-rtl-final" } */
+/* { dg-require-effective-target arm_neon_ok } */
+
+typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8)));
+void bar (int8x8_t, int8x8_t);
+
+void
+foo (int8x8_t x, int8x8_t y)
+{
+ bar (y, x);
+}
+
+void foo2 (int8x8_t x)
+{
+  int8x8_t y;
+  bar (y, x);
+}
+
+/* Check that these 64-bit moves are done in SI.  */
+/* { dg-final { scan-rtl-dump "_movsi_vfp" "final" } } */