mips.md (addsi3, adddi3): Use scratch register to add register to non-constant into sp.

* config/mips/mips.md (addsi3, adddi3): Use scratch register to
add register to non-constant into sp.

From-SVN: r50897

gcc/ChangeLog

 2002-03-16  Alexandre Oliva  <aoliva@redhat.com>
 
+	* config/mips/mips.md (addsi3, adddi3): Use scratch register to
+	add register to non-constant into sp.
+
 	* config/mips/mips-protos.h (embedded_pic_fnaddr_reg): New.
 	* config/mips/mips.h (embedded_pic_fnaddr_rtx): Lose.
 	(mips16_gp_pseudo_rtx): Lose.

gcc/config/mips/mips.md

@@ -614,6 +614,27 @@
       && GET_CODE (operands[2]) == CONST_INT
       && INTVAL (operands[2]) == -32768)
     operands[2] = force_reg (SImode, operands[2]);
+
+  /* If a large stack adjustment was forced into a register, we may be
+     asked to generate rtx such as:
+
+	(set (reg:SI sp) (plus:SI (reg:SI sp) (reg:SI pseudo)))
+
+     but no such instruction is available in mips16.  Handle it by
+     using a temporary.  */
+  if (TARGET_MIPS16
+      && REGNO (operands[0]) == STACK_POINTER_REGNUM
+      && ((GET_CODE (operands[1]) == REG
+	   && REGNO (operands[1]) != STACK_POINTER_REGNUM)
+	  || GET_CODE (operands[2]) != CONST_INT))
+    {
+      rtx tmp = gen_reg_rtx (SImode);
+
+      emit_move_insn (tmp, operands[1]);
+      emit_insn (gen_addsi3 (tmp, tmp, operands[2]));
+      emit_move_insn (operands[0], tmp);
+      DONE;
+    }
 }")
 
 (define_insn "addsi3_internal"
@@ -777,6 +798,27 @@
       && INTVAL (operands[2]) == -32768)
     operands[2] = force_reg (DImode, operands[2]);
 
+  /* If a large stack adjustment was forced into a register, we may be
+     asked to generate rtx such as:
+
+	(set (reg:DI sp) (plus:DI (reg:DI sp) (reg:DI pseudo)))
+
+     but no such instruction is available in mips16.  Handle it by
+     using a temporary.  */
+  if (TARGET_MIPS16
+      && REGNO (operands[0]) == STACK_POINTER_REGNUM
+      && ((GET_CODE (operands[1]) == REG
+	   && REGNO (operands[1]) != STACK_POINTER_REGNUM)
+	  || GET_CODE (operands[2]) != CONST_INT))
+    {
+      rtx tmp = gen_reg_rtx (DImode);
+
+      emit_move_insn (tmp, operands[1]);
+      emit_insn (gen_addsi3 (tmp, tmp, operands[2]));
+      emit_move_insn (operands[0], tmp);
+      DONE;
+    }
+
   if (TARGET_64BIT)
     {
       emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],