Eliminate trailing whitespace

From-SVN: r128605

gcc/config/i386/athlon.md

 ;; AMD Athlon Scheduling
 ;;
 ;; The Athlon does contain three pipelined FP units, three integer units and
-;; three address generation units. 
+;; three address generation units.
 ;;
 ;; The predecode logic is determining boundaries of instructions in the 64
 ;; byte cache line. So the cache line straddling problem of K6 might be issue
@@ -206,7 +206,7 @@
 			      (and (eq_attr "type" "imul")
 				   (and (eq_attr "mode" "HI")
 					(eq_attr "memory" "none,unknown"))))
-			 "athlon-vector,athlon-ieu0,athlon-mult,nothing,athlon-ieu0")			 
+			 "athlon-vector,athlon-ieu0,athlon-mult,nothing,athlon-ieu0")
 (define_insn_reservation "athlon_imul_mem" 8
 			 (and (eq_attr "cpu" "athlon")
 			      (and (eq_attr "type" "imul")
@@ -328,7 +328,7 @@
 					(eq_attr "memory" "both"))))
 			 "athlon-direct,athlon-load,
 			  athlon-ieu,athlon-store,
-			  athlon-store")			  
+			  athlon-store")
 
 (define_insn_reservation "athlon_ivector_both" 6
 			 (and (eq_attr "cpu" "athlon,k8,generic64")
@@ -617,7 +617,7 @@
 			 (and (eq_attr "cpu" "amdfam10")
 			      (and (eq_attr "type" "mmxmov")
 				   (eq_attr "memory" "load")))
-			 "athlon-direct,athlon-fploadk8, athlon-fany")			 
+			 "athlon-direct,athlon-fploadk8, athlon-fany")
 (define_insn_reservation "athlon_mmxssest" 3
 			 (and (eq_attr "cpu" "k8,generic64")
 			      (and (eq_attr "type" "mmxmov,ssemov")
@@ -926,7 +926,7 @@
 				   (and (eq_attr "amdfam10_decode" "double")
 					(and (eq_attr "mode" "SF,DF")
 					     (eq_attr "memory" "load")))))
-			 "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")			 
+			 "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
 ;; cvtsi2sd reg,reg is double decoded (vector on Athlon)
 (define_insn_reservation "athlon_sseicvt_cvtsi2sd_k8" 11
 			 (and (eq_attr "cpu" "k8,athlon,generic64")
@@ -1115,7 +1115,7 @@
 (define_insn_reservation "athlon_ssemulvector_amdfam10" 4
 			 (and (eq_attr "cpu" "amdfam10")
 			      (eq_attr "type" "ssemul"))
-			 "athlon-direct,athlon-fpsched,athlon-fmul")			 
+			 "athlon-direct,athlon-fpsched,athlon-fmul")
 ;; divsd timings.  divss is faster
 (define_insn_reservation "athlon_ssediv_load" 20
 			 (and (eq_attr "cpu" "athlon")
@@ -1148,7 +1148,7 @@
 			 (and (eq_attr "cpu" "amdfam10")
 			      (and (eq_attr "type" "ssediv")
 				   (eq_attr "memory" "load")))
-			 "athlon-direct,athlon-fploadk8,athlon-fmul*17")			 
+			 "athlon-direct,athlon-fploadk8,athlon-fmul*17")
 (define_insn_reservation "athlon_ssedivvector" 39
 			 (and (eq_attr "cpu" "athlon")
 			      (eq_attr "type" "ssediv"))

gcc/config/i386/constraints.md

@@ -18,7 +18,7 @@
 ;; <http://www.gnu.org/licenses/>.
 
 ;;; Unused letters:
-;;;     B     H           TU W   
+;;;     B     H           TU W
 ;;;           h jk          vw  z
 
 ;; Integer register constraints.
@@ -129,7 +129,7 @@
        (match_test "IN_RANGE (ival, 0, 3)")))
 
 (define_constraint "N"
-  "Unsigned 8-bit integer constant (for @code{in} and @code{out} 
+  "Unsigned 8-bit integer constant (for @code{in} and @code{out}
    instructions)."
   (and (match_code "const_int")
        (match_test "IN_RANGE (ival, 0, 255)")))

gcc/config/i386/i386.c

@@ -2011,7 +2011,7 @@ override_options (void)
       {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
       {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
       {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
-      {"nocona", PROCESSOR_NOCONA, (PTA_64BIT 
+      {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
 				    | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 				    | PTA_CX16 | PTA_NO_SAHF)},
       {"core2", PROCESSOR_CORE2, (PTA_64BIT
@@ -2181,7 +2181,7 @@ override_options (void)
     ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
   else
     ix86_arch_specified = 1;
-  
+
   if (!strcmp (ix86_arch_string, "generic"))
     error ("generic CPU can be used only for -mtune= switch");
   if (!strncmp (ix86_arch_string, "generic", 7))
@@ -4558,7 +4558,7 @@ function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
   else
     /* Most things go in %eax.  */
     regno = 0;
-  
+
   /* Override FP return register with %xmm0 for local functions when
      SSE math is enabled or for functions with sseregparm attribute.  */
   if ((fn || fntype) && (mode == SFmode || mode == DFmode))
@@ -4746,7 +4746,7 @@ ix86_return_in_memory (const_tree type)
    but differs notably in that when MMX is available, 8-byte vectors
    are returned in memory, rather than in MMX registers.  */
 
-int 
+int
 ix86_sol10_return_in_memory (const_tree type)
 {
   int size;
@@ -4889,7 +4889,7 @@ setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
   ix86_save_varrargs_registers = 1;
   /* We need 16-byte stack alignment to save SSE registers.  If user
      asked for lower preferred_stack_boundary, lets just hope that he knows
-     what he is doing and won't varargs SSE values.  
+     what he is doing and won't varargs SSE values.
 
      We also may end up assuming that only 64bit values are stored in SSE
      register let some floating point program work.  */
@@ -19794,7 +19794,7 @@ ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
 
 	  gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
 
-	  if (optimize 
+	  if (optimize
 	      || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
 	      || num_memory > 1)
 	    op = force_reg (mode, op);
@@ -21295,7 +21295,7 @@ ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
 	  || n != 4)
 	return NULL_TREE;
       break;
-    
+
     default:
       return NULL_TREE;
     }
@@ -24944,7 +24944,7 @@ bool ix86_sse5_valid_op_p (rtx operands[], rtx insn, int num, bool uses_oc0, int
 
       /* format, example pmacsdd:
 	 xmm1, xmm2, xmm3/mem, xmm1
-      
+
          For the integer multiply/add instructions be more restrictive and
          require operands[2] and operands[3] to be the memory operands.  */
       else
@@ -25044,7 +25044,7 @@ static const struct attribute_spec ix86_attribute_table[] =
 };
 
 /* Implement targetm.vectorize.builtin_vectorization_cost.  */
-static int 
+static int
 x86_builtin_vectorization_cost (bool runtime_test)
 {
   /* If the branch of the runtime test is taken - i.e. - the vectorized

gcc/config/i386/i386.h

@@ -75,9 +75,9 @@ enum stringop_alg
    When size is unknown, the UNKNOWN_SIZE alg is used.  When size is
    known at compile time or estimated via feedback, the SIZE array
    is walked in order until MAX is greater then the estimate (or -1
-   means infinity).  Corresponding ALG is used then.  
+   means infinity).  Corresponding ALG is used then.
    For example initializer:
-    {{256, loop}, {-1, rep_prefix_4_byte}}		
+    {{256, loop}, {-1, rep_prefix_4_byte}}
    will use loop for blocks smaller or equal to 256 bytes, rep prefix will
    be used otherwise.  */
 struct stringop_algs
@@ -153,7 +153,7 @@ struct processor_costs {
                                    scalar-to-vector operation.  */
   const int vec_to_scalar_cost;    /* Cost of vect-to-scalar operation.  */
   const int scalar_to_vec_cost;    /* Cost of scalar-to-vector operation.  */
-  const int vec_align_load_cost;   /* Cost of aligned vector load.  */ 
+  const int vec_align_load_cost;   /* Cost of aligned vector load.  */
   const int vec_unalign_load_cost; /* Cost of unaligned vector load.  */
   const int vec_store_cost;        /* Cost of vector store.  */
   const int cond_taken_branch_cost;    /* Cost of taken branch for vectorizer
@@ -375,7 +375,7 @@ enum ix86_arch_indices {
 
   X86_ARCH_LAST
 };
-  
+
 extern unsigned int ix86_arch_features[X86_ARCH_LAST];
 
 #define TARGET_CMOVE		ix86_arch_features[X86_ARCH_CMOVE]
@@ -2507,7 +2507,7 @@ struct machine_function GTY(())
 #define TARG_SCALAR_STORE_COST          ix86_cost->scalar_store_cost
 
 /* Cost of any vector operation, excluding load, store or vector to scalar
-   operation.  */ 
+   operation.  */
 #undef TARG_VEC_STMT_COST
 #define TARG_VEC_STMT_COST              ix86_cost->vec_stmt_cost
 

gcc/config/i386/i386.md

@@ -158,7 +158,7 @@
 
    ; For SSE4A support
    (UNSPEC_EXTRQI               130)
-   (UNSPEC_EXTRQ                131)   
+   (UNSPEC_EXTRQ                131)
    (UNSPEC_INSERTQI             132)
    (UNSPEC_INSERTQ              133)
 
@@ -1166,7 +1166,7 @@
    (set_attr "mode" "SI")])
 
 ;; Pentium Pro can do steps 1 through 3 in one go.
-;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes) 
+;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes)
 (define_insn "*cmpfp_i_mixed"
   [(set (reg:CCFP FLAGS_REG)
 	(compare:CCFP (match_operand 0 "register_operand" "f,x")
@@ -1476,7 +1476,7 @@
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "double")])   
+   (set_attr "amdfam10_decode" "double")])
 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -1594,7 +1594,7 @@
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "double")])   
+   (set_attr "amdfam10_decode" "double")])
 
 ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
 (define_insn "*swaphi_2"
@@ -1770,7 +1770,7 @@
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
 (define_insn "*swapqi_2"
@@ -2343,7 +2343,7 @@
    (set_attr "mode" "DI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "double")])   
+   (set_attr "amdfam10_decode" "double")])
 
 (define_expand "movti"
   [(set (match_operand:TI 0 "nonimmediate_operand" "")
@@ -3950,7 +3950,7 @@
   [(set (match_operand:DF 0 "register_operand" "")
         (float_extend:DF
 	  (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size 
+  "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
    && reload_completed && SSE_REG_P (operands[0])"
    [(set (match_dup 2)
 	 (float_extend:V2DF
@@ -3978,7 +3978,7 @@
       emit_insn (gen_sse_unpcklps (operands[3], operands[3], operands[3]));
     }
   else
-    emit_insn (gen_vec_setv4sf_0 (operands[3], 
+    emit_insn (gen_vec_setv4sf_0 (operands[3],
 				  CONST0_RTX (V4SFmode), operands[1]));
 })
 
@@ -4086,7 +4086,7 @@
   [(set (match_operand:SF 0 "register_operand" "")
         (float_truncate:SF
 	  (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size 
+  "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
    && reload_completed && SSE_REG_P (operands[0])"
    [(set (match_dup 2)
 	 (vec_concat:V4SF
@@ -4756,7 +4756,7 @@
    (set_attr "mode" "HI")
    (set_attr "unit" "i387")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 ;; Conversion between fixed point and floating point.
 
@@ -4851,7 +4851,7 @@
 (define_insn "*floatsisf2_mixed_vector"
   [(set (match_operand:SF 0 "register_operand" "=x,f,?f")
 	(float:SF (match_operand:SI 1 "nonimmediate_operand" "x,m,r")))]
-  "TARGET_MIX_SSE_I387 && !flag_trapping_math 
+  "TARGET_MIX_SSE_I387 && !flag_trapping_math
    && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
   "@
    cvtdq2ps\t{%1, %0|%0, %1}
@@ -4914,7 +4914,7 @@
   "#"
   [(set_attr "type" "multi")])
 
-(define_split 
+(define_split
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
   "flag_trapping_math
@@ -4929,7 +4929,7 @@
   emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode), operands[1]));
 })
 
-(define_split 
+(define_split
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:SI 1 "register_operand" "")))]
   "flag_trapping_math
@@ -5042,7 +5042,7 @@
    (set_attr "amdfam10_decode" "double")
    (set_attr "fp_int_src" "true")])
 
-(define_split 
+(define_split
   [(set (match_operand:DF 0 "register_operand" "")
 	(float:DF (match_operand:SI 1 "memory_operand" "")))]
   "TARGET_USE_VECTOR_CONVERTS && reload_completed
@@ -7483,11 +7483,11 @@
   "TARGET_64BIT"
   "")
 
-;; On AMDFAM10 
+;; On AMDFAM10
 ;; IMUL reg64, reg64, imm8 	Direct
 ;; IMUL reg64, mem64, imm8 	VectorPath
 ;; IMUL reg64, reg64, imm32 	Direct
-;; IMUL reg64, mem64, imm32 	VectorPath 
+;; IMUL reg64, mem64, imm32 	VectorPath
 ;; IMUL reg64, reg64 		Direct
 ;; IMUL reg64, mem64 		Direct
 
@@ -7517,7 +7517,7 @@
 	(cond [(and (eq_attr "alternative" "0,1")
 		    (match_operand 1 "memory_operand" ""))
 		  (const_string "vector")]
-	      (const_string "direct")))	      
+	      (const_string "direct")))
    (set_attr "mode" "DI")])
 
 (define_expand "mulsi3"
@@ -7528,7 +7528,7 @@
   ""
   "")
 
-;; On AMDFAM10 
+;; On AMDFAM10
 ;; IMUL reg32, reg32, imm8 	Direct
 ;; IMUL reg32, mem32, imm8 	VectorPath
 ;; IMUL reg32, reg32, imm32 	Direct
@@ -7561,7 +7561,7 @@
 	(cond [(and (eq_attr "alternative" "0,1")
 		    (match_operand 1 "memory_operand" ""))
 		  (const_string "vector")]
-	      (const_string "direct")))	      
+	      (const_string "direct")))
    (set_attr "mode" "SI")])
 
 (define_insn "*mulsi3_1_zext"
@@ -7591,7 +7591,7 @@
 	(cond [(and (eq_attr "alternative" "0,1")
 		    (match_operand 1 "memory_operand" ""))
 		  (const_string "vector")]
-	      (const_string "direct")))	      
+	      (const_string "direct")))
    (set_attr "mode" "SI")])
 
 (define_expand "mulhi3"
@@ -7659,7 +7659,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "direct")))
-   (set_attr "amdfam10_decode" "direct")        
+   (set_attr "amdfam10_decode" "direct")
    (set_attr "mode" "QI")])
 
 (define_expand "umulqihi3"
@@ -7711,7 +7711,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "direct")))
-   (set_attr "amdfam10_decode" "direct")        
+   (set_attr "amdfam10_decode" "direct")
    (set_attr "mode" "QI")])
 
 (define_expand "umulditi3"
@@ -7738,7 +7738,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
+   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "DI")])
 
 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
@@ -7766,7 +7766,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
+   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "SI")])
 
 (define_expand "mulditi3"
@@ -7820,7 +7820,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
+   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "SI")])
 
 (define_expand "umuldi3_highpart"
@@ -7857,7 +7857,7 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
+   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "DI")])
 
 (define_expand "umulsi3_highpart"
@@ -10991,7 +10991,7 @@
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 (define_expand "x86_64_shift_adj"
   [(set (reg:CCZ FLAGS_REG)
@@ -11209,7 +11209,7 @@
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 (define_expand "x86_shift_adj_1"
   [(set (reg:CCZ FLAGS_REG)
@@ -11971,7 +11971,7 @@
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "amdfam10_decode" "vector")])
 
 (define_expand "ashrdi3"
   [(set (match_operand:DI 0 "shiftdi_operand" "")
@@ -16606,7 +16606,7 @@
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
-   (set_attr "athlon_decode" "direct")   
+   (set_attr "athlon_decode" "direct")
    (set_attr "amdfam10_decode" "direct")])
 
 (define_insn "*rsqrtsf2_sse"
@@ -19734,7 +19734,7 @@
 ;; SSE5 conditional move
 (define_insn "*sse5_pcmov_<mode>"
   [(set (match_operand:MODEF 0 "register_operand" "=x,x,x,x")
-	(if_then_else:MODEF 
+	(if_then_else:MODEF
 	  (match_operand:MODEF 1 "nonimmediate_operand" "xm,x,0,0")
 	  (match_operand:MODEF 2 "nonimmediate_operand" "0,0,x,xm")
 	  (match_operand:MODEF 3 "vector_move_operand" "x,xm,xm,x")))]

gcc/config/i386/mmx.md

@@ -22,7 +22,7 @@
 ;; the same register file, and 3dNOW! adds a number of extensions to
 ;; the base integer MMX isa.
 
-;; Note!  Except for the basic move instructions, *all* of these 
+;; Note!  Except for the basic move instructions, *all* of these
 ;; patterns are outside the normal optabs namespace.  This is because
 ;; use of these registers requires the insertion of emms or femms
 ;; instructions to return to normal fpu mode.  The compiler doesn't
@@ -301,7 +301,7 @@
   "pfrsqrt\\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmx")
    (set_attr "mode" "V2SF")])
-		
+
 (define_insn "mmx_rsqit1v2sf3"
   [(set (match_operand:V2SF 0 "register_operand" "=y")
 	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
@@ -1429,4 +1429,4 @@
   "TARGET_3DNOW"
   "femms"
   [(set_attr "type" "mmx")
-   (set_attr "memory" "none")]) 
+   (set_attr "memory" "none")])

gcc/config/i386/ppro.md

@@ -78,7 +78,7 @@
 ;;    but still in only one cycle.
 ;;  - a complex (microcode) instruction can also only be decoded by
 ;;    decoder 0, and this takes an unspecified number of cycles.
-;;    
+;;
 ;; The goal is to schedule such that we have a few-one-one uops sequence
 ;; in each cycle, to decode as many instructions per cycle as possible.
 (define_cpu_unit "decoder0" "ppro_decoder")

gcc/config/i386/sse.md

@@ -602,7 +602,7 @@
    (set_attr "mode" "SF")])
 
 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
-;; isn't really correct, as those rtl operators aren't defined when 
+;; isn't really correct, as those rtl operators aren't defined when
 ;; applied to NaNs.  Hopefully the optimizers won't get too smart on us.
 
 (define_expand "smaxv4sf3"
@@ -754,7 +754,7 @@
 	(vec_concat:V4SF
 	  (vec_concat:V2SF
 	    (plus:SF
-	      (vec_select:SF 
+	      (vec_select:SF
 		(match_operand:V4SF 1 "register_operand" "0")
 		(parallel [(const_int 0)]))
 	      (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
@@ -781,7 +781,7 @@
 	(vec_concat:V4SF
 	  (vec_concat:V2SF
 	    (minus:SF
-	      (vec_select:SF 
+	      (vec_select:SF
 		(match_operand:V4SF 1 "register_operand" "0")
 		(parallel [(const_int 0)]))
 	      (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
@@ -2290,7 +2290,7 @@
    (set_attr "mode" "DF")])
 
 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
-;; isn't really correct, as those rtl operators aren't defined when 
+;; isn't really correct, as those rtl operators aren't defined when
 ;; applied to NaNs.  Hopefully the optimizers won't get too smart on us.
 
 (define_expand "smaxv2df3"
@@ -3527,7 +3527,7 @@
   emit_insn (gen_sse2_punpcklbw (t[3], operands[2], operands[2]));
 
   /* Multiply words.  The end-of-line annotations here give a picture of what
-     the output of that instruction looks like.  Dot means don't care; the 
+     the output of that instruction looks like.  Dot means don't care; the
      letters are the bytes of the result with A being the most significant.  */
   emit_insn (gen_mulv8hi3 (gen_lowpart (V8HImode, t[4]), /* .A.B.C.D.E.F.G.H */
 			   gen_lowpart (V8HImode, t[0]),
@@ -3569,8 +3569,8 @@
 (define_expand "smulv8hi3_highpart"
   [(set (match_operand:V8HI 0 "register_operand" "")
         (truncate:V8HI
-          (lshiftrt:V8SI 
-            (mult:V8SI 
+          (lshiftrt:V8SI
+            (mult:V8SI
               (sign_extend:V8SI
                 (match_operand:V8HI 1 "nonimmediate_operand" ""))
               (sign_extend:V8SI
@@ -3578,7 +3578,7 @@
             (const_int 16))))]
   "TARGET_SSE2"
   "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
-  
+
 (define_insn "*smulv8hi3_highpart"
   [(set (match_operand:V8HI 0 "register_operand" "=x")
 	(truncate:V8HI
@@ -3776,7 +3776,7 @@
 			       thirtytwo));
   emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t3),
 			       gen_lowpart (TImode, op2),
-			       thirtytwo)); 
+			       thirtytwo));
   /* Multiply elements 3 and 1.  */
   emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t4),
 				     t2, t3));
@@ -4011,8 +4011,8 @@
 })
 
 (define_expand "udot_prodv4si"
-  [(match_operand:V2DI 0 "register_operand" "") 
-   (match_operand:V4SI 1 "register_operand" "") 
+  [(match_operand:V2DI 0 "register_operand" "")
+   (match_operand:V4SI 1 "register_operand" "")
    (match_operand:V4SI 2 "register_operand" "")
    (match_operand:V2DI 3 "register_operand" "")]
   "TARGET_SSE2"
@@ -4875,7 +4875,7 @@
 		     (const_int 9)  (const_int 25)
 		     (const_int 10) (const_int 26)
 		     (const_int 11) (const_int 27)
-		     (const_int 12) (const_int 28) 
+		     (const_int 12) (const_int 28)
 		     (const_int 13) (const_int 29)
 		     (const_int 14) (const_int 30)
 		     (const_int 15) (const_int 31)])))]
@@ -5283,7 +5283,7 @@
   "TARGET_SSE"
   "#"
   "&& reload_completed
-   && (TARGET_INTER_UNIT_MOVES 
+   && (TARGET_INTER_UNIT_MOVES
        || MEM_P (operands [0])
        || !GENERAL_REGNO_P (true_regnum (operands [0])))"
   [(set (match_dup 0) (match_dup 1))]
@@ -5343,7 +5343,7 @@
 	  (parallel [(const_int 0)])))]
   "TARGET_SSE
    && reload_completed
-   && (TARGET_INTER_UNIT_MOVES 
+   && (TARGET_INTER_UNIT_MOVES
        || MEM_P (operands [0])
        || !GENERAL_REGNO_P (true_regnum (operands [0])))"
   [(set (match_dup 0) (match_dup 1))]
@@ -5839,7 +5839,7 @@
    (set_attr "prefix_data16" "1")
    (set_attr "mode" "TI")])
 
-;; The correct representation for this is absolutely enormous, and 
+;; The correct representation for this is absolutely enormous, and
 ;; surely not generally useful.
 (define_insn "sse2_psadbw"
   [(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -6641,7 +6641,7 @@
 
 (define_insn "sse4a_vmmovntv2df"
   [(set (match_operand:DF 0 "memory_operand" "=m")
-        (unspec:DF [(vec_select:DF 
+        (unspec:DF [(vec_select:DF
                       (match_operand:V2DF 1 "register_operand" "x")
                       (parallel [(const_int 0)]))]
                    UNSPEC_MOVNT))]
@@ -6661,7 +6661,7 @@
 
 (define_insn "sse4a_vmmovntv4sf"
   [(set (match_operand:SF 0 "memory_operand" "=m")
-	(unspec:SF [(vec_select:SF 
+	(unspec:SF [(vec_select:SF
 	              (match_operand:V4SF 1 "register_operand" "x")
 		      (parallel [(const_int 0)]))]
 		   UNSPEC_MOVNT))]
@@ -7893,7 +7893,7 @@
 ;; SSE5 parallel XMM conditional moves
 (define_insn "sse5_pcmov_<mode>"
   [(set (match_operand:SSEMODE 0 "register_operand" "=x,x,x,x,x,x")
-	(if_then_else:SSEMODE 
+	(if_then_else:SSEMODE
 	  (match_operand:SSEMODE 3 "nonimmediate_operand" "0,0,xm,xm,0,0")
 	  (match_operand:SSEMODE 1 "vector_move_operand" "x,xm,0,x,C,x")
 	  (match_operand:SSEMODE 2 "vector_move_operand" "xm,x,x,0,x,C")))]

gcc/config/i386/sync.md

@@ -34,7 +34,7 @@
 ;; ??? It would be possible to use cmpxchg8b on pentium for DImode
 ;; changes.  It's complicated because the insn uses ecx:ebx as the
 ;; new value; note that the registers are reversed from the order
-;; that they'd be in with (reg:DI 2 ecx).  Similarly for TImode 
+;; that they'd be in with (reg:DI 2 ecx).  Similarly for TImode
 ;; data in 64-bit mode.
 
 (define_expand "sync_compare_and_swap<mode>"