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riscv-gcc-1
Commit 4e76acd2 by Uros Bizjak Committed by Uros Bizjak
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constraints.md (Y3): New register constraint. 

	* config/i386/constraints.md (Y3): New register constraint.
	* config/i386/sse.md (*vec_interleave_highv2df): Merge with
	*sse3_interleave_highv2df and *sse2_interleave_highv2df.
	(*vec_interleave_lowv2df): Merge with *sse3_interleave_lowv2df and
	*sse2_interleave_lowv2df.

From-SVN: r174580
parent 288f605f
Showing with 24 additions and 47 deletions
gcc/ChangeLog
2011-06-02 Uros Bizjak <ubizjak@gmail.com>
* config/i386/constraints.md (Y3): New register constraint.
* config/i386/sse.md (*vec_interleave_highv2df): Merge with
*sse3_interleave_highv2df and *sse2_interleave_highv2df.
(*vec_interleave_lowv2df): Merge with *sse3_interleave_lowv2df and
*sse2_interleave_lowv2df.
2011-06-02 Julian Brown <julian@codesourcery.com>
* config/arm/arm-cores.def (cortex-a5): Use cortex_a5 tuning.
......@@ -33,12 +41,12 @@
2011-06-02 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (standard_sse_constant_p) <case 1>:
Simplify switch statement.
* config/i386/i386.c (standard_sse_constant_p) <case 1>: Simplify
switch statement.
* config/i386/i386.md (*movdf_internal_rex64) <case 8,9,10>: Ditto.
(*movdf_internal) <case 6,7,8>: Ditto.
* config/i386/constraints.md (Y4): New constraint.
* config/i386/constraints.md (Y4): New register constraint.
* config/i386/sse.md (vec_set<mode>_0): Merge with
*vec_set<mode>_0_sse4_1 and *vec_set<mode>_0_sse2.
(*vec_extractv2di_1): Merge from *vec_extractv2di_1_sse2 and
......
gcc/config/i386/constraints.md
......@@ -99,6 +99,9 @@
(define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE2 is enabled.")
(define_register_constraint "Y3" "TARGET_SSE3 ? SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE3 is enabled.")
(define_register_constraint "Y4" "TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE4_1 is enabled.")
......
gcc/config/i386/sse.md
......@@ -3804,15 +3804,15 @@
operands[2] = force_reg (V2DFmode, operands[2]);
})
(define_insn "*sse3_interleave_highv2df"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,m")
(define_insn "*vec_interleave_highv2df"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,Y3,x,x,m")
(vec_select:V2DF
(vec_concat:V4DF
(match_operand:V2DF 1 "nonimmediate_operand" " 0,x,o,o,o,x")
(match_operand:V2DF 2 "nonimmediate_operand" " x,x,1,0,x,0"))
(match_operand:V2DF 1 "nonimmediate_operand" " 0,x,o ,o,o,x")
(match_operand:V2DF 2 "nonimmediate_operand" " x,x,1 ,0,x,0"))
(parallel [(const_int 1)
(const_int 3)])))]
"TARGET_SSE3 && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
"TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
"@
unpckhpd\t{%2, %0|%0, %2}
vunpckhpd\t{%2, %1, %0|%0, %1, %2}
......@@ -3826,23 +3826,6 @@
(set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")
(set_attr "mode" "V2DF,V2DF,V2DF,V1DF,V1DF,V1DF")])
(define_insn "*sse2_interleave_highv2df"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
(vec_select:V2DF
(vec_concat:V4DF
(match_operand:V2DF 1 "nonimmediate_operand" " 0,o,x")
(match_operand:V2DF 2 "nonimmediate_operand" " x,0,0"))
(parallel [(const_int 1)
(const_int 3)])))]
"TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
"@
unpckhpd\t{%2, %0|%0, %2}
movlpd\t{%H1, %0|%0, %H1}
movhpd\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog,ssemov,ssemov")
(set_attr "prefix_data16" "*,1,1")
(set_attr "mode" "V2DF,V1DF,V1DF")])
;; Recall that the 256-bit unpck insns only shuffle within their lanes.
(define_expand "avx_movddup256"
[(set (match_operand:V4DF 0 "register_operand" "")
......@@ -3923,15 +3906,15 @@
operands[1] = force_reg (V2DFmode, operands[1]);
})
(define_insn "*sse3_interleave_lowv2df"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,o")
(define_insn "*vec_interleave_lowv2df"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,Y3,x,x,o")
(vec_select:V2DF
(vec_concat:V4DF
(match_operand:V2DF 1 "nonimmediate_operand" " 0,x,m,0,x,0")
(match_operand:V2DF 2 "nonimmediate_operand" " x,x,1,m,m,x"))
(match_operand:V2DF 1 "nonimmediate_operand" " 0,x,m ,0,x,0")
(match_operand:V2DF 2 "nonimmediate_operand" " x,x,1 ,m,m,x"))
(parallel [(const_int 0)
(const_int 2)])))]
"TARGET_SSE3 && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
"TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
"@
unpcklpd\t{%2, %0|%0, %2}
vunpcklpd\t{%2, %1, %0|%0, %1, %2}
......@@ -3945,23 +3928,6 @@
(set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")
(set_attr "mode" "V2DF,V2DF,V2DF,V1DF,V1DF,V1DF")])
(define_insn "*sse2_interleave_lowv2df"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o")
(vec_select:V2DF
(vec_concat:V4DF
(match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0")
(match_operand:V2DF 2 "nonimmediate_operand" " x,m,x"))
(parallel [(const_int 0)
(const_int 2)])))]
"TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
"@
unpcklpd\t{%2, %0|%0, %2}
movhpd\t{%2, %0|%0, %2}
movlpd\t{%2, %H0|%H0, %2}"
[(set_attr "type" "sselog,ssemov,ssemov")
(set_attr "prefix_data16" "*,1,1")
(set_attr "mode" "V2DF,V1DF,V1DF")])
(define_split
[(set (match_operand:V2DF 0 "memory_operand" "")
(vec_select:V2DF
......
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