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lvzhengyang
riscv-gcc-1
Commits
4e5f1329
Commit
4e5f1329
authored
Aug 25, 1999
by
Jeff Law
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Plain Diff
Fix typo.
From-SVN: r28852
parent
5722d61c
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4 changed files
with
5 additions
and
5 deletions
+5
-5
gcc/NEWS
+1
-1
gcc/config/ns32k/ns32k.md
+2
-2
gcc/f/ffe.texi
+1
-1
gcc/tm.texi
+1
-1
No files found.
gcc/NEWS
View file @
4e5f1329
...
@@ -68,7 +68,7 @@ Build time improvements for targets which support lots of sched parameters
...
@@ -68,7 +68,7 @@ Build time improvements for targets which support lots of sched parameters
(alpha and mips primarily).
(alpha and mips primarily).
Compile time for certain programs using large constant initializers has been
Compile time for certain programs using large constant initializers has been
improved (
e
ffects glibc significantly).
improved (
a
ffects glibc significantly).
Plus an incredible number of infrastructure changes, warning fixes, bugfixes
Plus an incredible number of infrastructure changes, warning fixes, bugfixes
and local optimizations.
and local optimizations.
...
...
gcc/config/ns32k/ns32k.md
View file @
4e5f1329
...
@@ -1335,7 +1335,7 @@
...
@@ -1335,7 +1335,7 @@
DONE;
DONE;
}")
}")
;; deiw wants two hi's in sep
e
rate registers or else they can be adjacent
;; deiw wants two hi's in sep
a
rate registers or else they can be adjacent
;; in memory. DI mode will ensure two registers are available, but if we
;; in memory. DI mode will ensure two registers are available, but if we
;; want to allow memory as an operand we would need SI mode. There is no
;; want to allow memory as an operand we would need SI mode. There is no
;; way to do this, so just restrict operand 0 and 1 to be in registers.
;; way to do this, so just restrict operand 0 and 1 to be in registers.
...
@@ -1392,7 +1392,7 @@
...
@@ -1392,7 +1392,7 @@
DONE;
DONE;
}")
}")
;; deib wants two qi's in sep
e
rate registers or else they can be adjacent
;; deib wants two qi's in sep
a
rate registers or else they can be adjacent
;; in memory. DI mode will ensure two registers are available, but if we
;; in memory. DI mode will ensure two registers are available, but if we
;; want to allow memory as an operand we would need HI mode. There is no
;; want to allow memory as an operand we would need HI mode. There is no
;; way to do this, so just restrict operand 0 and 1 to be in registers.
;; way to do this, so just restrict operand 0 and 1 to be in registers.
...
...
gcc/f/ffe.texi
View file @
4e5f1329
...
@@ -640,7 +640,7 @@ and
...
@@ -640,7 +640,7 @@ and
except
it
also
provides
automatic
conversion
of
tabs
except
it
also
provides
automatic
conversion
of
tabs
and
ignoring
of
newline
-
related
carriage
returns
.
and
ignoring
of
newline
-
related
carriage
returns
.
It
also
e
ffects
the
``
pure
visual
''
model
,
It
also
a
ffects
the
``
pure
visual
''
model
,
by
which
is
meant
that
a
user
viewing
his
code
by
which
is
meant
that
a
user
viewing
his
code
in
a
typical
text
editor
in
a
typical
text
editor
(
assuming
it
'
s
not
preprocessed
via
@code{
g77stripcard
}
or
similar
)
(
assuming
it
'
s
not
preprocessed
via
@code{
g77stripcard
}
or
similar
)
...
...
gcc/tm.texi
View file @
4e5f1329
...
@@ -2981,7 +2981,7 @@ stack.
...
@@ -2981,7 +2981,7 @@ stack.
@item
LOAD_ARGS_REVERSED
@item
LOAD_ARGS_REVERSED
If
defined
,
the
order
in
which
arguments
are
loaded
into
their
If
defined
,
the
order
in
which
arguments
are
loaded
into
their
respective
argument
registers
is
reversed
so
that
the
last
respective
argument
registers
is
reversed
so
that
the
last
argument
is
loaded
first
.
This
macro
only
e
ffects
arguments
argument
is
loaded
first
.
This
macro
only
a
ffects
arguments
passed
in
registers
.
passed
in
registers
.
@end
table
@end
table
...
...
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