Commit 4dff12bf by J"orn Rennecke Committed by Joern Rennecke

sh.md (attribute "type"): Add nil.

        * sh.md (attribute "type"): Add nil.
        (movsi_ie): y/y alternative is type nil.
        (movsf_ie): Replace ry/yr/X alternative by r/y/X , y/r/X and y/y/X
        alternatives.
        (movsf_ie+1): Delete.

From-SVN: r16575
parent 218c2cdb
Tue Nov 18 23:03:30 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
* sh.md (attribute "type"): Add nil.
(movsi_ie): y/y alternative is type nil.
(movsf_ie): Replace ry/yr/X alternative by r/y/X , y/r/X and y/y/X
alternatives.
(movsf_ie+1): Delete.
Tue Nov 18 15:39:59 1997 Jim Wilson <wilson@cygnus.com> Tue Nov 18 15:39:59 1997 Jim Wilson <wilson@cygnus.com>
* mips/mips.c (save_restore_insns): If gp_offset or fp_offset are * mips/mips.c (save_restore_insns): If gp_offset or fp_offset are
......
...@@ -101,9 +101,10 @@ ...@@ -101,9 +101,10 @@
;; fp floating point ;; fp floating point
;; fdiv floating point divide (or square root) ;; fdiv floating point divide (or square root)
;; gp_fpul move between general purpose register and fpul ;; gp_fpul move between general purpose register and fpul
;; nil no-op move, will be deleted.
(define_attr "type" (define_attr "type"
"cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,pstore,pcload,pcload_si,rte,sfunc,call,fp,fdiv,gp_fpul" "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,pstore,pcload,pcload_si,rte,sfunc,call,fp,fdiv,gp_fpul,nil"
(const_string "other")) (const_string "other"))
; If a conditional branch destination is within -252..258 bytes away ; If a conditional branch destination is within -252..258 bytes away
...@@ -1847,7 +1848,7 @@ ...@@ -1847,7 +1848,7 @@
lds %1,%0 lds %1,%0
sts %1,%0 sts %1,%0
! move optimized away" ! move optimized away"
[(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,pcload_si,gp_fpul,gp_fpul,other") [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,pcload_si,gp_fpul,gp_fpul,nil")
(set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")]) (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
(define_insn "movsi_i_lowpart" (define_insn "movsi_i_lowpart"
...@@ -2118,12 +2119,15 @@ ...@@ -2118,12 +2119,15 @@
sts %1,%0" sts %1,%0"
[(set_attr "type" "move,move,pcload,load,store,move,move")]) [(set_attr "type" "move,move,pcload,load,store,move,move")])
;; We may not split the ry/yr/XX alternatives to movsi_ie, since
;; update_flow_info would not know where to put REG_EQUAL notes
;; when the destination changes mode.
(define_insn "movsf_ie" (define_insn "movsf_ie"
[(set (match_operand:SF 0 "general_movdst_operand" [(set (match_operand:SF 0 "general_movdst_operand"
"=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,ry") "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,y")
(match_operand:SF 1 "general_movsrc_operand" (match_operand:SF 1 "general_movsrc_operand"
"f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,yr")) "f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y"))
(clobber (match_scratch:SI 2 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X"))] (clobber (match_scratch:SI 2 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X"))]
"TARGET_SH3E "TARGET_SH3E
&& (arith_reg_operand (operands[0], SFmode) && (arith_reg_operand (operands[0], SFmode)
...@@ -2143,23 +2147,11 @@ ...@@ -2143,23 +2147,11 @@
flds %1,fpul flds %1,fpul
lds.l %1,%0 lds.l %1,%0
# #
#" sts %1,%0
[(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,*") lds %1,%0
(set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,*,*")]) ! move optimized away"
[(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,nil")
(define_split (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,*,2,2,0")])
[(set (match_operand:SF 0 "register_operand" "ry")
(match_operand:SF 1 "register_operand" "ry"))
(clobber (match_scratch:SI 2 "X"))]
"reload_completed
&& true_regnum (operands[0]) < FIRST_FP_REG
&& true_regnum (operands[1]) < FIRST_FP_REG"
[(set (match_dup 0) (match_dup 1))]
"
{
operands[0] = gen_rtx (REG, SImode, true_regnum (operands[0]));
operands[1] = gen_rtx (REG, SImode, true_regnum (operands[1]));
}")
(define_split (define_split
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SF 0 "register_operand" "")
......
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