Skip to content

R
riscv-gcc-1
Commit 4d4447b5 by Peter Bergner Committed by Peter Bergner
Options

rs6000.c (invalid_e500_subreg, [...]): Handle DDmode and TDmode similarly to DFmode and TFmode. 

	* config/rs6000/rs6000.c (invalid_e500_subreg,
	rs6000_legitimate_offset_address_p, legitimate_lo_sum_address_p,
	rs6000_legitimize_address, rs6000_legitimize_reload_address,
	rs6000_legitimate_address, function_arg_advance,
	spe_build_register_parallel, rs6000_spe_function_arg,
	rs6000_split_multireg_move, spe_func_has_64bit_regs_p,
	emit_frame_save, gen_frame_mem_offset, rs6000_function_value,
	rs6000_libcall_value, rs6000_dwarf_register_span): Handle DDmode and
	TDmode similarly to DFmode and TFmode.
	* config/rs6000/rs6000.h (LOCAL_ALIGNMENT, MEMBER_TYPE_FORCES_BLK,
	DATA_ALIGNMENT, CLASS_MAX_NREGS, CANNOT_CHANGE_MODE_CLASS): Likewise.

	* gcc.dg/dfp/ddmode-ice.c: New test.

From-SVN: r130296
parent b7cfd8a4
Showing with 131 additions and 39 deletions
gcc/ChangeLog
2007-11-19 Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/rs6000.c (invalid_e500_subreg,
rs6000_legitimate_offset_address_p, legitimate_lo_sum_address_p,
rs6000_legitimize_address, rs6000_legitimize_reload_address,
rs6000_legitimate_address, function_arg_advance,
spe_build_register_parallel, rs6000_spe_function_arg,
rs6000_split_multireg_move, spe_func_has_64bit_regs_p,
emit_frame_save, gen_frame_mem_offset, rs6000_function_value,
rs6000_libcall_value, rs6000_dwarf_register_span): Handle DDmode and
TDmode similarly to DFmode and TFmode.
* config/rs6000/rs6000.h (LOCAL_ALIGNMENT, MEMBER_TYPE_FORCES_BLK,
DATA_ALIGNMENT, CLASS_MAX_NREGS, CANNOT_CHANGE_MODE_CLASS): Likewise.
2007-11-19 Eric Botcazou <ebotcazou@adacore.com>
* stor-layout.c (lang_adjust_rli): Delete.
gcc/config/rs6000/rs6000.h
......@@ -559,7 +559,8 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
that the object would ordinarily have. */
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
(TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \
(TARGET_E500_DOUBLE \
&& (TYPE_MODE (TYPE) == DFmode || TYPE_MODE (TYPE) == DDmode)) ? 64 : \
((TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE \
&& SPE_VECTOR_MODE (TYPE_MODE (TYPE))) || (TARGET_PAIRED_FLOAT \
&& TREE_CODE (TYPE) == VECTOR_TYPE \
......@@ -585,7 +586,7 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
fit into 1, whereas DI still needs two. */
#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
|| (TARGET_E500_DOUBLE && (MODE) == DFmode))
|| (TARGET_E500_DOUBLE && ((MODE) == DFmode || (MODE) == DDmode)))
/* A bit-field declared as `int' forces `int' alignment for the struct. */
#define PCC_BITFIELD_TYPE_MATTERS 1
......@@ -604,7 +605,8 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == VECTOR_TYPE ? ((TARGET_SPE_ABI \
|| TARGET_PAIRED_FLOAT) ? 64 : 128) \
: (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \
: (TARGET_E500_DOUBLE \
&& (TYPE_MODE (TYPE) == DFmode || TYPE_MODE (TYPE) == DDmode)) ? 64 \
: TREE_CODE (TYPE) == ARRAY_TYPE \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
......@@ -1178,7 +1180,8 @@ enum reg_class
#define CLASS_MAX_NREGS(CLASS, MODE) \
(((CLASS) == FLOAT_REGS) \
? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
: (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \
: (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS \
&& ((MODE) == DFmode || (MODE) == DDmode)) \
? 1 \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
......@@ -1192,6 +1195,8 @@ enum reg_class
: (((TARGET_E500_DOUBLE \
&& ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \
|| (((TO) == TFmode) + ((FROM) == TFmode)) == 1 \
|| (((TO) == DDmode) + ((FROM) == DDmode)) == 1 \
|| (((TO) == TDmode) + ((FROM) == TDmode)) == 1 \
|| (((TO) == DImode) + ((FROM) == DImode)) == 1)) \
|| (TARGET_SPE \
&& (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \
......@@ -1717,11 +1722,11 @@ typedef struct rs6000_args
refers to a constant pool entry of an address (or the sum of it
plus a constant), a short (16-bit signed) constant plus a register,
the sum of two registers, or a register indirect, possibly with an
auto-increment. For DFmode and DImode with a constant plus register,
we must ensure that both words are addressable or PowerPC64 with offset
word aligned.
auto-increment. For DFmode, DDmode and DImode with a constant plus
register, we must ensure that both words are addressable or PowerPC64
with offset word aligned.
For modes spanning multiple registers (DFmode in 32-bit GPRs,
For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
32-bit DImode, TImode), indexed addressing cannot be used because
adjacent memory cells are accessed by adding word-sized offsets
during assembly output. */
......
gcc/testsuite/ChangeLog
2007-11-19 Peter Bergner <bergner@vnet.ibm.com>
* gcc.dg/dfp/ddmode-ice.c: New test.
2007-11-19 Eric Botcazou <ebotcazou@libertysurf.fr>
PR tree-optimization/34036
gcc/testsuite/gcc.dg/dfp/ddmode-ice.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-std=gnu99 -O1" } */
/* This used to result in an ICE. */
_Decimal64 y[258][258];
_Decimal64 dd[258][258];
_Decimal64 ry[258][258];
_Decimal64
foo (void)
{
int i;
int j;
int m;
int im;
int jm;
int ip;
int jp;
int i2m;
int i1p;
_Decimal64 a;
_Decimal64 b;
_Decimal64 c;
_Decimal64 qi;
_Decimal64 qj;
_Decimal64 xx;
_Decimal64 yx;
_Decimal64 xy;
_Decimal64 yy;
_Decimal64 rel;
_Decimal64 qxx;
_Decimal64 qyy;
_Decimal64 qxy;
do
{
jp = j + 1;
for (i = i1p; i <= i2m; i++)
{
ip = i + 1;
yx = y[ip][j] - y[im][j];
yy = y[i][jp] - y[i][jm];
a = 0.25dd * (xy * xy + yy * yy);
b = 0.25dd * (xx * xx + yx * yx);
c = 0.125dd * (xx * xy + yx * yy);
qj = 0.0dd;
dd[i][m] = b + a * rel + b;
qxx = y[ip][j] - 2.0dd * y[i][j] + y[im][j];
qyy = y[i][jp] - 2.0dd * y[i][j] + y[i][jm];
qxy = y[ip][jp] - y[ip][jm] - y[im][jp] + y[im][jm];
ry[i][m] = a * qxx + b * qyy - c * qxy + yx * qi + yy * qj;
}
}
while (1);
}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment