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riscv-gcc-1
Commit 4d259d3b by Uros Bizjak Committed by Uros Bizjak
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sse.md (vec_set<VI4F_256_512:mode>_0): Use nonimmediate_operand as operand 2 predicate. 

	* config/i386/sse.md (vec_set<VI4F_256_512:mode>_0): Use
	nonimmediate_operand as operand 2 predicate.
	(vec_set<VF2_512_256:mode>_0): Ditto.
	(vec_set<VI8_AVX_AVX512F:mode>_0): Ditto.
	(*vec_concatv2si): Remove alternative 2.
	(*vec_concatv4si_0): Use vm constraint for alternative 0.
	(*vec_concatv4si_0): Remove preferred_for_speed attribute.
	(vec_concatv2di): Split alternatives 4,5,6 to ...
	(*vec_concatv2di_0) ... new pattern.

testsuite/ChangeLog:

	* gcc.target/i386/sse2-init-v2di-2.c (dg-final): Update scan string.

From-SVN: r268855
parent f83fad40
Showing with 55 additions and 40 deletions
gcc/ChangeLog
2019-02-13 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (vec_set<VI4F_256_512:mode>_0): Use
nonimmediate_operand as operand 2 predicate.
(vec_set<VF2_512_256:mode>_0): Ditto.
(vec_set<VI8_AVX_AVX512F:mode>_0): Ditto.
(*vec_concatv2si): Remove alternative 2.
(*vec_concatv4si_0): Use vm constraint for alternative 0.
(*vec_concatv4si_0): Remove preferred_for_speed attribute.
(vec_concatv2di): Split alternatives 4,5,6 to ...
(*vec_concatv2di_0) ... new pattern.
2019-02-13 Wilco Dijkstra <wdijkstr@arm.com> 2019-02-13 Wilco Dijkstra <wdijkstr@arm.com>
PR target/89190 PR target/89190
......
gcc/config/i386/sse.md
...@@ -7417,7 +7417,7 @@ ...@@ -7417,7 +7417,7 @@
[(set (match_operand:VI4F_256_512 0 "register_operand" "=v,v,v") [(set (match_operand:VI4F_256_512 0 "register_operand" "=v,v,v")
(vec_merge:VI4F_256_512 (vec_merge:VI4F_256_512
(vec_duplicate:VI4F_256_512 (vec_duplicate:VI4F_256_512
(match_operand:<ssescalarmode> 2 "general_operand" "v,m,r")) (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "v,m,r"))
(match_operand:VI4F_256_512 1 "const0_operand" "C,C,C") (match_operand:VI4F_256_512 1 "const0_operand" "C,C,C")
(const_int 1)))] (const_int 1)))]
"TARGET_AVX" "TARGET_AVX"
...@@ -9669,7 +9669,7 @@ ...@@ -9669,7 +9669,7 @@
[(set (match_operand:VF2_512_256 0 "register_operand" "=v") [(set (match_operand:VF2_512_256 0 "register_operand" "=v")
(vec_merge:VF2_512_256 (vec_merge:VF2_512_256
(vec_duplicate:VF2_512_256 (vec_duplicate:VF2_512_256
(match_operand:<ssescalarmode> 2 "general_operand" "xm")) (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "xm"))
(match_operand:VF2_512_256 1 "const0_operand" "C") (match_operand:VF2_512_256 1 "const0_operand" "C")
(const_int 1)))] (const_int 1)))]
"TARGET_AVX" "TARGET_AVX"
...@@ -14573,22 +14573,21 @@ ...@@ -14573,22 +14573,21 @@
;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
;; alternatives pretty much forces the MMX alternative to be chosen. ;; alternatives pretty much forces the MMX alternative to be chosen.
(define_insn "*vec_concatv2si" (define_insn "*vec_concatv2si"
[(set (match_operand:V2SI 0 "register_operand" "=x,x ,*y,x,x,*y,*y") [(set (match_operand:V2SI 0 "register_operand" "=x,x ,x,x,*y,*y")
(vec_concat:V2SI (vec_concat:V2SI
(match_operand:SI 1 "nonimmediate_operand" " 0,rm,rm,0,m, 0,*rm") (match_operand:SI 1 "nonimmediate_operand" " 0,rm,0,m, 0,rm")
(match_operand:SI 2 "reg_or_0_operand" " x,C ,C, x,C,*y,C")))] (match_operand:SI 2 "reg_or_0_operand" " x,C ,x,C,*y,C")))]
"TARGET_SSE && !TARGET_SSE4_1" "TARGET_SSE && !TARGET_SSE4_1"
"@ "@
punpckldq\t{%2, %0|%0, %2} punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1} movd\t{%1, %0|%0, %1}
movd\t{%1, %0|%0, %1}
unpcklps\t{%2, %0|%0, %2} unpcklps\t{%2, %0|%0, %2}
movss\t{%1, %0|%0, %1} movss\t{%1, %0|%0, %1}
punpckldq\t{%2, %0|%0, %2} punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1}" movd\t{%1, %0|%0, %1}"
[(set_attr "isa" "sse2,sse2,sse2,*,*,*,*") [(set_attr "isa" "sse2,sse2,*,*,*,*")
(set_attr "type" "sselog,ssemov,mmxmov,sselog,ssemov,mmxcvt,mmxmov") (set_attr "type" "sselog,ssemov,sselog,ssemov,mmxcvt,mmxmov")
(set_attr "mode" "TI,TI,DI,V4SF,SF,DI,DI")]) (set_attr "mode" "TI,TI,V4SF,SF,DI,DI")])
(define_insn "*vec_concatv4si" (define_insn "*vec_concatv4si"
[(set (match_operand:V4SI 0 "register_operand" "=x,v,x,x,v") [(set (match_operand:V4SI 0 "register_operand" "=x,v,x,x,v")
...@@ -14610,7 +14609,7 @@ ...@@ -14610,7 +14609,7 @@
(define_insn "*vec_concatv4si_0" (define_insn "*vec_concatv4si_0"
[(set (match_operand:V4SI 0 "register_operand" "=v,x") [(set (match_operand:V4SI 0 "register_operand" "=v,x")
(vec_concat:V4SI (vec_concat:V4SI
(match_operand:V2SI 1 "nonimmediate_operand" "xm,?!*y") (match_operand:V2SI 1 "nonimmediate_operand" "vm,?!*y")
(match_operand:V2SI 2 "const0_operand" " C,C")))] (match_operand:V2SI 2 "const0_operand" " C,C")))]
"TARGET_SSE2" "TARGET_SSE2"
"@ "@
...@@ -14618,30 +14617,22 @@ ...@@ -14618,30 +14617,22 @@
movq2dq\t{%1, %0|%0, %1}" movq2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov") [(set_attr "type" "ssemov")
(set_attr "prefix" "maybe_vex,orig") (set_attr "prefix" "maybe_vex,orig")
(set_attr "mode" "TI") (set_attr "mode" "TI")])
(set (attr "preferred_for_speed")
(if_then_else (eq_attr "alternative" "1")
(symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
(symbol_ref "true")))])
;; movd instead of movq is required to handle broken assemblers.
(define_insn "vec_concatv2di" (define_insn "vec_concatv2di"
[(set (match_operand:V2DI 0 "register_operand" [(set (match_operand:V2DI 0 "register_operand"
"=Yr,*x,x ,v ,v,v ,x ,x,v ,x,x,v") "=Yr,*x,x ,v ,x,v ,x,x,v")
(vec_concat:V2DI (vec_concat:V2DI
(match_operand:DI 1 "nonimmediate_operand" (match_operand:DI 1 "register_operand"
" 0, 0,x ,Yv,r,vm,?!*y,0,Yv,0,0,v") " 0, 0,x ,Yv,0,Yv,0,0,v")
(match_operand:DI 2 "nonimm_or_0_operand" (match_operand:DI 2 "nonimmediate_operand"
" rm,rm,rm,rm,C ,C ,C ,x,Yv,x,m,m")))] " rm,rm,rm,rm,x,Yv,x,m,m")))]
"TARGET_SSE" "TARGET_SSE"
"@ "@
pinsrq\t{$1, %2, %0|%0, %2, 1} pinsrq\t{$1, %2, %0|%0, %2, 1}
pinsrq\t{$1, %2, %0|%0, %2, 1} pinsrq\t{$1, %2, %0|%0, %2, 1}
vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1} vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1}
vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1} vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1}
* return HAVE_AS_IX86_INTERUNIT_MOVQ ? \"%vmovq\t{%1, %0|%0, %1}\" : \"%vmovd\t{%1, %0|%0, %1}\";
%vmovq\t{%1, %0|%0, %1}
movq2dq\t{%1, %0|%0, %1}
punpcklqdq\t{%2, %0|%0, %2} punpcklqdq\t{%2, %0|%0, %2}
vpunpcklqdq\t{%2, %1, %0|%0, %1, %2} vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
movlhps\t{%2, %0|%0, %2} movlhps\t{%2, %0|%0, %2}
...@@ -14655,22 +14646,18 @@ ...@@ -14655,22 +14646,18 @@
(eq_attr "alternative" "3") (eq_attr "alternative" "3")
(const_string "x64_avx512dq") (const_string "x64_avx512dq")
(eq_attr "alternative" "4") (eq_attr "alternative" "4")
(const_string "x64_sse2")
(eq_attr "alternative" "5,6")
(const_string "sse2")
(eq_attr "alternative" "7")
(const_string "sse2_noavx") (const_string "sse2_noavx")
(eq_attr "alternative" "8,11") (eq_attr "alternative" "5,8")
(const_string "avx") (const_string "avx")
] ]
(const_string "noavx"))) (const_string "noavx")))
(set (attr "type") (set (attr "type")
(if_then_else (if_then_else
(eq_attr "alternative" "0,1,2,3,7,8") (eq_attr "alternative" "0,1,2,3,4,5")
(const_string "sselog") (const_string "sselog")
(const_string "ssemov"))) (const_string "ssemov")))
(set (attr "prefix_rex") (set (attr "prefix_rex")
(if_then_else (eq_attr "alternative" "0,1,2,3,4") (if_then_else (eq_attr "alternative" "0,1,2,3")
(const_string "1") (const_string "1")
(const_string "*"))) (const_string "*")))
(set (attr "prefix_extra") (set (attr "prefix_extra")
...@@ -14686,18 +14673,30 @@ ...@@ -14686,18 +14673,30 @@
(const_string "vex") (const_string "vex")
(eq_attr "alternative" "3") (eq_attr "alternative" "3")
(const_string "evex") (const_string "evex")
(eq_attr "alternative" "4,5") (eq_attr "alternative" "5,8")
(const_string "maybe_vex")
(eq_attr "alternative" "8,11")
(const_string "maybe_evex") (const_string "maybe_evex")
] ]
(const_string "orig"))) (const_string "orig")))
(set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,TI,TI,V4SF,V2SF,V2SF") (set_attr "mode" "TI,TI,TI,TI,TI,TI,V4SF,V2SF,V2SF")])
(define_insn "*vec_concatv2di_0"
[(set (match_operand:V2DI 0 "register_operand" "=v,v ,x")
(vec_concat:V2DI
(match_operand:DI 1 "nonimmediate_operand" " r,vm,?!*y")
(match_operand:DI 2 "const0_operand" " C,C ,C")))]
"TARGET_SSE2"
"@
* return HAVE_AS_IX86_INTERUNIT_MOVQ ? \"%vmovq\t{%1, %0|%0, %1}\" : \"%vmovd\t{%1, %0|%0, %1}\";
%vmovq\t{%1, %0|%0, %1}
movq2dq\t{%1, %0|%0, %1}"
[(set_attr "isa" "x64,*,*")
(set_attr "type" "ssemov")
(set_attr "prefix_rex" "1,*,*")
(set_attr "prefix" "maybe_vex,maybe_vex,orig")
(set_attr "mode" "TI")
(set (attr "preferred_for_speed") (set (attr "preferred_for_speed")
(cond [(eq_attr "alternative" "4") (cond [(eq_attr "alternative" "0")
(symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC") (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
(eq_attr "alternative" "6")
(symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
] ]
(symbol_ref "true")))]) (symbol_ref "true")))])
...@@ -14706,7 +14705,7 @@ ...@@ -14706,7 +14705,7 @@
[(set (match_operand:VI8_AVX_AVX512F 0 "register_operand" "=v,v") [(set (match_operand:VI8_AVX_AVX512F 0 "register_operand" "=v,v")
(vec_merge:VI8_AVX_AVX512F (vec_merge:VI8_AVX_AVX512F
(vec_duplicate:VI8_AVX_AVX512F (vec_duplicate:VI8_AVX_AVX512F
(match_operand:<ssescalarmode> 2 "general_operand" "r,vm")) (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "r,vm"))
(match_operand:VI8_AVX_AVX512F 1 "const0_operand" "C,C") (match_operand:VI8_AVX_AVX512F 1 "const0_operand" "C,C")
(const_int 1)))] (const_int 1)))]
"TARGET_AVX" "TARGET_AVX"
......
gcc/testsuite/ChangeLog
2019-02-13 Uroš Bizjak <ubizjak@gmail.com>
* gcc.target/i386/sse2-init-v2di-2.c (dg-final): Update scan string.
2019-02-13 Marek Polacek <polacek@redhat.com> 2019-02-13 Marek Polacek <polacek@redhat.com>
PR c++/89297 - ICE with OVERLOAD in template. PR c++/89297 - ICE with OVERLOAD in template.
......
gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
...@@ -10,4 +10,4 @@ test (long long b) ...@@ -10,4 +10,4 @@ test (long long b)
return _mm_cvtsi64_si128 (b); return _mm_cvtsi64_si128 (b);
} }
/* { dg-final { scan-assembler-times "vec_concatv2di/4" 1 } } */ /* { dg-final { scan-assembler-times "\\*vec_concatv2di_0/0" 1 } } */
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