2008-xx-xx Richard Sandiford <rdsandiford@goolemail.com> Peter Fuerst <post@pfrst.de>

gcc/
2008-xx-xx  Richard Sandiford  <rdsandiford@goolemail.com>
	    Peter Fuerst  <post@pfrst.de>

	* doc/invoke.texi: Document -mr10k-cache-barrier=.
	* doc/extend.texi: Document __builtin_mips_cache.
	* config/mips/mips-ftypes.def: Add a (VOID, SI, CVPOINTER) entry.
	* config/mips/mips.opt (mr10k-cache-barrier=): New option.
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
	__GCC_HAVE_BUILTIN_MIPS_CACHE.
	(TARGET_CACHE_BUILTIN, ISA_HAS_CACHE): New macros.
	* config/mips/mips.c (mips_r10k_cache_barrier_setting): New enum.
	(set_push_mips_isas): New variable.
	(mips_r10k_cache_barrier): New variable.
	(cache): New availability predicate.
	(mips_builtins): Add an entry for __builtin_mips_cache.
	(mips_build_cvpointer_type): New function.
	(MIPS_ATYPE_CVPOINTER): New macro.
	(mips_prepare_builtin_arg): Only use the insn's mode if the rtx's
	mode is VOIDmode.
	(r10k_simplified_address_p, r10k_simplify_address)
	(r10k_uncached_address_p, r10k_safe_address_p)
	(r10k_needs_protection_p_1, r10k_needs_protection_p_store)
	(r10k_needs_protection_p_call, r10k_needs_protection_p)
	(r10k_insert_cache_barriers): New functions.
	(mips_reorg_process_insns): Delete cache barriers after a
	branch-likely instruction.
	(mips_reorg): Call r10k_insert_cache_barriers.
	(mips_handle_option): Handle OPT_mr10k_cache_barrier_.
	* config/mips/mips.md (UNSPEC_MIPS_CACHE): New constant.
	(UNSPEC_R10K_CACHE_BARRIER): Likewise.
	(mips_cache, r10k_cache_barrier): New define_insns.

gcc/testsuite/
	* gcc.target/mips/mips.exp (dg-mips-options): Make
	-mr10k-cache-barrier=* imply -mips3 or above.
	* gcc.target/mips/cache-1.c: New test.
	* gcc.target/mips/r10k-cache-barrier-1.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-2.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-3.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-4.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-5.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-6.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-7.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-8.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-9.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-10.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-11.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-12.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-13.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-14.c: Likewise.
	* gcc.target/mips/r10k-cache-barrier-15.c: Likewise.

From-SVN: r140055

gcc/ChangeLog

+2008-09-06  Richard Sandiford  <rdsandiford@goolemail.com>
+	    Peter Fuerst  <post@pfrst.de>
+
+	* doc/invoke.texi: Document -mr10k-cache-barrier=.
+	* doc/extend.texi: Document __builtin_mips_cache.
+	* config/mips/mips-ftypes.def: Add a (VOID, SI, CVPOINTER) entry.
+	* config/mips/mips.opt (mr10k-cache-barrier=): New option.
+	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
+	__GCC_HAVE_BUILTIN_MIPS_CACHE.
+	(TARGET_CACHE_BUILTIN, ISA_HAS_CACHE): New macros.
+	* config/mips/mips.c (mips_r10k_cache_barrier_setting): New enum.
+	(set_push_mips_isas): New variable.
+	(mips_r10k_cache_barrier): New variable.
+	(cache): New availability predicate.
+	(mips_builtins): Add an entry for __builtin_mips_cache.
+	(mips_build_cvpointer_type): New function.
+	(MIPS_ATYPE_CVPOINTER): New macro.
+	(mips_prepare_builtin_arg): Only use the insn's mode if the rtx's
+	mode is VOIDmode.
+	(r10k_simplified_address_p, r10k_simplify_address)
+	(r10k_uncached_address_p, r10k_safe_address_p)
+	(r10k_needs_protection_p_1, r10k_needs_protection_p_store)
+	(r10k_needs_protection_p_call, r10k_needs_protection_p)
+	(r10k_insert_cache_barriers): New functions.
+	(mips_reorg_process_insns): Delete cache barriers after a
+	branch-likely instruction.
+	(mips_reorg): Call r10k_insert_cache_barriers.
+	(mips_handle_option): Handle OPT_mr10k_cache_barrier_.
+	* config/mips/mips.md (UNSPEC_MIPS_CACHE): New constant.
+	(UNSPEC_R10K_CACHE_BARRIER): Likewise.
+	(mips_cache, r10k_cache_barrier): New define_insns.
+
 2008-09-06  Richard Sandiford  <rdsandiford@googlemail.com>
 
 	* ira-int.h (ira_zero_hard_reg_set, ira_one_hard_reg_set): Delete.

gcc/config/mips/mips-ftypes.def

@@ -120,6 +120,7 @@ DEF_MIPS_FTYPE (2, (V8QI, V4HI, V4HI))
 DEF_MIPS_FTYPE (1, (V8QI, V8QI))
 DEF_MIPS_FTYPE (2, (V8QI, V8QI, V8QI))
 
+DEF_MIPS_FTYPE (2, (VOID, SI, CVPOINTER))
 DEF_MIPS_FTYPE (2, (VOID, SI, SI))
 DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
 DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))

gcc/config/mips/mips.h

@@ -563,6 +563,9 @@ enum mips_code_readable_setting {
 									\
       if (mips_abi == ABI_EABI)						\
 	builtin_define ("__mips_eabi");					\
+									\
+      if (TARGET_CACHE_BUILTIN)						\
+	builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE");		\
     }									\
   while (0)
 
@@ -1020,6 +1023,12 @@ enum mips_code_readable_setting {
 
 /* ISA includes the pop instruction.  */
 #define ISA_HAS_POP		TARGET_OCTEON
+
+/* The CACHE instruction is available in non-MIPS16 code.  */
+#define TARGET_CACHE_BUILTIN (mips_isa >= 3)
+
+/* The CACHE instruction is available.  */
+#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
 
 /* Add -G xx support.  */
 

gcc/config/mips/mips.md

@@ -247,6 +247,9 @@
    (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN   531)
    (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN  532)
    (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN  533)
+
+   (UNSPEC_MIPS_CACHE		600)
+   (UNSPEC_R10K_CACHE_BARRIER	601)
   ]
 )
 
@@ -4722,6 +4725,25 @@
 }
   [(set_attr "length" "20")])
 
+;; Cache operations for R4000-style caches.
+(define_insn "mips_cache"
+  [(set (mem:BLK (scratch))
+	(unspec:BLK [(match_operand:SI 0 "const_int_operand")
+		     (match_operand:QI 1 "address_operand" "p")]
+		    UNSPEC_MIPS_CACHE))]
+  "ISA_HAS_CACHE"
+  "cache\t%X0,%a1")
+
+;; Similar, but with the operands hard-coded to an R10K cache barrier
+;; operation.  We keep the pattern distinct so that we can identify
+;; cache operations inserted by -mr10k-cache-barrier=, and so that
+;; the operation is never inserted into a delay slot.
+(define_insn "r10k_cache_barrier"
+  [(set (mem:BLK (scratch))
+	(unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
+  "ISA_HAS_CACHE"
+  "cache\t0x14,0(%$)"
+  [(set_attr "can_delay" "no")])
 
 ;; Block moves, see mips.c for more details.
 ;; Argument 0 is the destination

gcc/config/mips/mips.opt

@@ -236,6 +236,10 @@ mpaired-single
 Target Report Mask(PAIRED_SINGLE_FLOAT)
 Use paired-single floating-point instructions
 
+mr10k-cache-barrier=
+Target Joined RejectNegative
+-mr10k-cache-barrier=SETTING	Specify when r10k cache barriers should be inserted
+
 mshared
 Target Report Var(TARGET_SHARED) Init(1)
 When generating -mabicalls code, make the code suitable for use in shared libraries

gcc/doc/extend.texi

@@ -6985,6 +6985,7 @@ instructions, but allow the compiler to schedule those calls.
 * MIPS DSP Built-in Functions::
 * MIPS Paired-Single Support::
 * MIPS Loongson Built-in Functions::
+* Other MIPS Built-in Functions::
 * picoChip Built-in Functions::
 * PowerPC AltiVec Built-in Functions::
 * SPARC VIS Built-in Functions::
@@ -9440,6 +9441,18 @@ implementing assertions.
 
 @end table
 
+@node Other MIPS Built-in Functions
+@subsection Other MIPS Built-in Functions
+
+GCC provides other MIPS-specific built-in functions:
+
+@table @code
+@item void __builtin_mips_cache (int @var{op}, const volatile void *@var{addr})
+Insert a @samp{cache} instruction with operands @var{op} and @var{addr}.
+GCC defines the preprocessor macro @code{___GCC_HAVE_BUILTIN_MIPS_CACHE}
+when this function is available.
+@end table
+
 @node PowerPC AltiVec Built-in Functions
 @subsection PowerPC AltiVec Built-in Functions
 

gcc/doc/invoke.texi

@@ -12808,6 +12808,73 @@ Work around certain SB-1 CPU core errata.
 (This flag currently works around the SB-1 revision 2
 ``F1'' and ``F2'' floating point errata.)
 
+@item -mr10k-cache-barrier=@var{setting}
+@opindex mr10k-cache-barrier
+Specify whether GCC should insert cache barriers to avoid the
+side-effects of speculation on R10K processors.
+
+In common with many processors, the R10K tries to predict the outcome
+of a conditional branch and speculatively executes instructions from
+the ``taken'' branch.  It later aborts these instructions if the
+predicted outcome was wrong.  However, on the R10K, even aborted
+instructions can have side effects.
+
+This problem only affects kernel stores and, depending on the system,
+kernel loads.  As an example, a speculatively-executed store may load
+the target memory into cache and mark the cache line as dirty, even if
+the store itself is later aborted.  If a DMA operation writes to the
+same area of memory before the ``dirty'' line is flushed, the cached
+data will overwrite the DMA-ed data.  See the R10K processor manual
+for a full description, including other potential problems.
+
+One workaround is to insert cache barrier instructions before every memory
+access that might be speculatively executed and that might have side
+effects even if aborted.  @option{-mr10k-cache-barrier=@var{setting}}
+controls GCC's implementation of this workaround.  It assumes that
+aborted accesses to any byte in the following regions will not have
+side effects:
+
+@enumerate
+@item
+the memory occupied by the current function's stack frame;
+
+@item
+the memory occupied by an incoming stack argument;
+
+@item
+the memory occupied by an object with a link-time-constant address.
+@end enumerate
+
+It is the kernel's responsibility to ensure that speculative
+accesses to these regions are indeed safe.
+
+If the input program contains a function declaration such as:
+
+@smallexample
+void foo (void);
+@end smallexample
+
+then the implementation of @code{foo} must allow @code{j foo} and
+@code{jal foo} to be executed speculatively.  GCC honors this
+restriction for functions it compiles itself.  It expects non-GCC
+functions (such as hand-written assembly code) to do the same.
+
+The option has three forms:
+
+@table @gcctabopt
+@item -mr10k-cache-barrier=load-store
+Insert a cache barrier before a load or store that might be
+speculatively executed and that might have side effects even
+if aborted.
+
+@item -mr10k-cache-barrier=store
+Insert a cache barrier before a store that might be speculatively
+executed and that might have side effects even if aborted.
+
+@item -mr10k-cache-barrier=none
+Disable the insertion of cache barriers.  This is the default setting.
+@end table
+
 @item -mflush-func=@var{func}
 @itemx -mno-flush-func
 @opindex mflush-func

gcc/testsuite/ChangeLog

+2008-09-06  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* gcc.target/mips/mips.exp (dg-mips-options): Make
+	-mr10k-cache-barrier=* imply -mips3 or above.
+	* gcc.target/mips/cache-1.c: New test.
+	* gcc.target/mips/r10k-cache-barrier-1.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-2.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-3.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-4.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-5.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-6.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-7.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-8.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-9.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-10.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-11.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-12.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-13.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-14.c: Likewise.
+	* gcc.target/mips/r10k-cache-barrier-15.c: Likewise.
+
 2008-09-05  Daniel Kraft  <d@domob.eu>
 
 	PR fortran/35837

gcc/testsuite/gcc.target/mips/cache-1.c

+/* { dg-mips-options "-O2" } */
+
+void
+f1 (int *area)
+{
+  __builtin_mips_cache (20, area);
+}
+
+void
+f2 (const short *area)
+{
+  __builtin_mips_cache (24, area + 10);
+}
+
+void
+f3 (volatile unsigned int *area, int offset)
+{
+  __builtin_mips_cache (0, area + offset);
+}
+
+void
+f4 (const volatile unsigned char *area)
+{
+  __builtin_mips_cache (4, area - 80);
+}
+
+/* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x0,0\\(\\\$.\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */

gcc/testsuite/gcc.target/mips/mips.exp

@@ -238,6 +238,10 @@ proc dg-mips-options {args} {
 	    } else {
 		append flags " -msoft-float"
 	    }
+	} elseif {[regexp -- {^-mr10k-cache-barrier=(load|store)} $flag]
+		  && $mips_isa < 3
+		  && [lsearch -regexp $flags {^(-mips|-march)}] < 0} {
+	    append flags " -mips3"
 	}
     }
     foreach flag $flags {

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c

+/* { dg-mips-options "-O2 -mabi=64 -mr10k-cache-barrier=store" } */
+
+/* Test that stores to uncached addresses do not get unnecessary
+   cache barriers.  */
+
+#define TEST(ADDR)					\
+  NOMIPS16 void						\
+  test_##ADDR (int n)					\
+  {							\
+    while (n--)						\
+      {							\
+	*(volatile char *) (0x##ADDR##UL) = 1;		\
+	*(volatile short *) (0x##ADDR##UL + 2) = 2;	\
+	*(volatile int *) (0x##ADDR##UL + 4) = 0;	\
+      }							\
+  }
+
+TEST (9000000000000000)
+TEST (900000fffffffff8)
+
+TEST (9200000000000000)
+TEST (920000fffffffff8)
+
+TEST (9400000000000000)
+TEST (940000fffffffff8)
+
+TEST (9600000000000000)
+TEST (960000fffffffff8)
+
+TEST (b800000000000000)
+TEST (b80000fffffffff8)
+
+TEST (ba00000000000000)
+TEST (ba0000fffffffff8)
+
+TEST (bc00000000000000)
+TEST (bc0000fffffffff8)
+
+TEST (be00000000000000)
+TEST (be0000fffffffff8)
+
+TEST (ffffffffa0000000)
+TEST (ffffffffbffffff8)
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -mips4 -mbranch-likely -mno-abicalls" } */
+int bar (int);
+
+/* Test that code after a branch-likely does not get an unnecessary
+   cache barrier.  */
+
+NOMIPS16 void
+foo (int n, int *x)
+{
+  do
+    n = bar (n * 4 + 1);
+  while (n);
+  /* The preceding branch should be a branch likely, with the shift as
+     its delay slot.  We therefore don't need a cache barrier here.  */
+  x[0] = 0;
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
+
+/* Test that loads are not unnecessarily protected.  */
+
+int bar (int);
+
+NOMIPS16 void
+foo (int *ptr)
+{
+  *ptr = bar (*ptr);
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 1 } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=load-store -mno-abicalls" } */
+
+/* Test that loads are correctly protected.  */
+
+int bar (int);
+
+NOMIPS16 void
+foo (int *ptr)
+{
+  *ptr = bar (*ptr);
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store" } */
+
+/* Test that indirect calls are protected.  */
+
+int bar (int);
+
+NOMIPS16 void
+foo (void (*fn) (void), int x)
+{
+  if (x)
+    (*fn) ();
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 1 } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c

+/* { dg-do compile { target mips16_attribute } } */
+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store" } */
+/* { dg-add-options mips16_attribute } */
+
+/* Test that indirect calls are protected.  */
+
+MIPS16 void foo (void) { } /* { dg-message "sorry, unimplemented" } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -mips2" } */
+/* { dg-error "requires.*cache.*instruction" "" { target *-*-* } 0 } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c

+/* { dg-mips-options "-O2 -mabi=64 -mr10k-cache-barrier=store" } */
+
+/* Test that stores to constant cached addresses are protected
+   by cache barriers.  */
+
+#define TEST(ADDR)					\
+  NOMIPS16 void						\
+  test_##ADDR (int n)					\
+  {							\
+    *(volatile int *) (0x##ADDR##UL) = 1;		\
+  }
+
+TEST (8ffffffffffffffc)
+TEST (9000010000000000)
+
+TEST (91fffffffffffffc)
+TEST (9200010000000000)
+
+TEST (93fffffffffffffc)
+TEST (9500010000000000)
+
+TEST (95fffffffffffffc)
+TEST (9600010000000000)
+
+TEST (b7fffffffffffffc)
+TEST (b800010000000000)
+
+TEST (b9fffffffffffffc)
+TEST (ba00010000000000)
+
+TEST (bbfffffffffffffc)
+TEST (bc00010000000000)
+
+TEST (bdfffffffffffffc)
+TEST (be00010000000000)
+
+TEST (ffffffff9ffffffc)
+TEST (ffffffffc0000000)
+
+/* { dg-final { scan-assembler-times "\tcache\t" 18 } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
+
+/* Test that in-range stores to the frame are not protected by
+   cache barriers.  */
+
+void bar (int *x);
+
+NOMIPS16 void
+foo (int v)
+{
+  int x[0x100000];
+  bar (x);
+  x[0x20] = v;
+  bar (x);
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
+
+void bar (int *x);
+
+/* Test that out-of-range stores to the frame are protected by cache
+   barriers.  */
+
+NOMIPS16 void
+foo (int v)
+{
+  int x[8];
+  bar (x);
+  if (v & 1)
+    x[0x100] = 0;
+  if (v & 2)
+    x[-0x100] = 0;
+  bar (x);
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -mno-abicalls -mabi=64" } */
+
+/* Test that in-range stores to static objects do not get an unnecessary
+   cache barrier.  */
+
+int x[4];
+void bar (void);
+
+NOMIPS16 void
+foo (int n)
+{
+  while (n--)
+    {
+      x[3] = 1;
+      bar ();
+    }
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -mabi=64" } */
+
+int x[4];
+void bar (void);
+
+/* Test that out-of-range stores to static objects are protected by a
+   cache barrier.  */
+
+NOMIPS16 void
+foo (int n)
+{
+  while (n--)
+    {
+      x[4] = 1;
+      bar ();
+    }
+}
+
+/* { dg-final { scan-assembler "\tcache\t" } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
+
+void bar1 (void);
+void bar2 (void);
+void bar3 (void);
+
+NOMIPS16 void
+foo (int *x, int sel, int n)
+{
+  if (sel)
+    {
+      bar1 ();
+      x[0] = 1;
+    }
+  else
+    {
+      bar2 ();
+      x[1] = 0;
+    }
+  /* If there is one copy of this code, reached by two unconditional edges,
+     then it shouldn't need a third cache barrier.  */
+  x[2] = 2;
+  while (n--)
+    bar3 ();
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -G8" } */
+
+/* Test that in-range stores to components of static objects
+   do not get an unnecessary cache barrier.  */
+
+struct { struct { char i[4]; } a; struct { char j[4]; } b; } s;
+
+NOMIPS16 void
+foo (int sel)
+{
+  s.a.i[0] = 1;
+  s.b.j[3] = 100;
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */

gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c

+/* { dg-mips-options "-O2 -mr10k-cache-barrier=store -G8" } */
+
+/* Test that out-of-range stores to components of static objects
+   are protected by a cache barrier.  */
+
+struct { struct { char i[4]; } a; struct { char j[4]; } b; } s;
+
+NOMIPS16 void
+foo (int sel1, int sel2, int sel3)
+{
+  if (sel1)
+    s.a.i[8] = 1;
+  if (sel2)
+    s.b.j[4] = 100;
+  if (sel3)
+    s.a.i[-1] = 0;
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 3 } } */