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Commit 4d0a0237 by Charles Baylis Committed by Charles Baylis
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re PR target/63870 ([Aarch64] [ARM] Errors in use of NEON intrinsics are reported incorrectly) 

gcc/ChangeLog:

2015-07-22  Charles Baylis  <charles.baylis@linaro.org>

	PR target/63870
	* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
	Add qualifier_struct_load_store_lane_index.
	(aarch64_types_loadstruct_lane_qualifiers): Use
	qualifier_struct_load_store_lane_index for lane index argument for
	last argument.
	(aarch64_types_storestruct_lane_qualifiers): Ditto.
	(builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
	(aarch64_simd_expand_args): Add new argument describing mode of
	builtin. Check lane bounds for arguments with
	SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
	(aarch64_simd_expand_builtin): Emit error for incorrect lane indices
	if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
	(aarch64_simd_expand_builtin): Handle arguments with
	qualifier_struct_load_store_lane_index. Pass machine mode of builtin to
	aarch64_simd_expand_args.
	* config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and
	vst[234]_lane with BUILTIN_VALLDIF.
	* config/aarch64/aarch64-simd.md:
	(aarch64_vec_load_lanesoi_lane<mode>): Use VALLDIF iterator. Perform
	endianness reversal on lane index.
	(aarch64_vec_load_lanesci_lane<mode>): Ditto.
	(aarch64_vec_load_lanesxi_lane<mode>): Ditto.
	(vec_store_lanesoi_lane<mode>): Use VALLDIF iterator.
	(vec_store_lanesci_lane<mode>): Ditto.
	(vec_store_lanesxi_lane<mode>): Ditto.
	(aarch64_ld2_lane<mode>): Use VALLDIF iterator. Remove endianness
	reversal of lane index.
	(aarch64_ld3_lane<mode>): Ditto.
	(aarch64_ld4_lane<mode>): Ditto.
	(aarch64_st2_lane<mode>): Ditto.
	(aarch64_st3_lane<mode>): Ditto.
	(aarch64_st4_lane<mode>): Ditto.
	* config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter
	to qmode. Add new mode parameter. Update uses.
       	(__LD3_LANE_FUNC): Ditto.
	(__LD4_LANE_FUNC): Ditto.
	(__ST2_LANE_FUNC): Ditto.
	(__ST3_LANE_FUNC): Ditto.
	(__ST4_LANE_FUNC): Ditto.

gcc/testsuite/ChangeLog:

2015-07-22  Charles Baylis  <charles.baylis@linaro.org>

        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c: New
	test.

From-SVN: r226059
parent ebaec5f0
Showing with 1621 additions and 50 deletions
gcc/ChangeLog
2015-07-22 Charles Baylis <charles.baylis@linaro.org>
PR target/63870
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
Add qualifier_struct_load_store_lane_index.
(aarch64_types_loadstruct_lane_qualifiers): Use
qualifier_struct_load_store_lane_index for lane index argument for
last argument.
(aarch64_types_storestruct_lane_qualifiers): Ditto.
(builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(aarch64_simd_expand_args): Add new argument describing mode of
builtin. Check lane bounds for arguments with
SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(aarch64_simd_expand_builtin): Emit error for incorrect lane indices
if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(aarch64_simd_expand_builtin): Handle arguments with
qualifier_struct_load_store_lane_index. Pass machine mode of builtin to
aarch64_simd_expand_args.
* config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and
vst[234]_lane with BUILTIN_VALLDIF.
* config/aarch64/aarch64-simd.md:
(aarch64_vec_load_lanesoi_lane<mode>): Use VALLDIF iterator. Perform
endianness reversal on lane index.
(aarch64_vec_load_lanesci_lane<mode>): Ditto.
(aarch64_vec_load_lanesxi_lane<mode>): Ditto.
(vec_store_lanesoi_lane<mode>): Use VALLDIF iterator.
(vec_store_lanesci_lane<mode>): Ditto.
(vec_store_lanesxi_lane<mode>): Ditto.
(aarch64_ld2_lane<mode>): Use VALLDIF iterator. Remove endianness
reversal of lane index.
(aarch64_ld3_lane<mode>): Ditto.
(aarch64_ld4_lane<mode>): Ditto.
(aarch64_st2_lane<mode>): Ditto.
(aarch64_st3_lane<mode>): Ditto.
(aarch64_st4_lane<mode>): Ditto.
* config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter
to qmode. Add new mode parameter. Update uses.
(__LD3_LANE_FUNC): Ditto.
(__LD4_LANE_FUNC): Ditto.
(__ST2_LANE_FUNC): Ditto.
(__ST3_LANE_FUNC): Ditto.
(__ST4_LANE_FUNC): Ditto.
2015-07-22 Jonathan Wakely <jwakely@redhat.com>
* doc/invoke.texi (Language Independent Options): Rename node to
......
gcc/config/aarch64/aarch64-builtins.c
......@@ -114,7 +114,9 @@ enum aarch64_type_qualifiers
/* Polynomial types. */
qualifier_poly = 0x100,
/* Lane indices - must be in range, and flipped for bigendian. */
qualifier_lane_index = 0x200
qualifier_lane_index = 0x200,
/* Lane indices for single lane structure loads and stores. */
qualifier_struct_load_store_lane_index = 0x400
};
typedef struct
......@@ -216,7 +218,7 @@ aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
static enum aarch64_type_qualifiers
aarch64_types_loadstruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_const_pointer_map_mode,
qualifier_none, qualifier_none };
qualifier_none, qualifier_struct_load_store_lane_index };
#define TYPES_LOADSTRUCT_LANE (aarch64_types_loadstruct_lane_qualifiers)
static enum aarch64_type_qualifiers
......@@ -248,7 +250,7 @@ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
static enum aarch64_type_qualifiers
aarch64_types_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode,
qualifier_none, qualifier_none };
qualifier_none, qualifier_struct_load_store_lane_index };
#define TYPES_STORESTRUCT_LANE (aarch64_types_storestruct_lane_qualifiers)
#define CF0(N, X) CODE_FOR_aarch64_##N##X
......@@ -864,12 +866,14 @@ typedef enum
SIMD_ARG_COPY_TO_REG,
SIMD_ARG_CONSTANT,
SIMD_ARG_LANE_INDEX,
SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX,
SIMD_ARG_STOP
} builtin_simd_arg;
static rtx
aarch64_simd_expand_args (rtx target, int icode, int have_retval,
tree exp, builtin_simd_arg *args)
tree exp, builtin_simd_arg *args,
enum machine_mode builtin_mode)
{
rtx pat;
rtx op[SIMD_MAX_BUILTIN_ARGS + 1]; /* First element for result operand. */
......@@ -908,6 +912,19 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
op[opc] = copy_to_mode_reg (mode, op[opc]);
break;
case SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX:
gcc_assert (opc > 1);
if (CONST_INT_P (op[opc]))
{
aarch64_simd_lane_bounds (op[opc], 0,
GET_MODE_NUNITS (builtin_mode),
exp);
/* Keep to GCC-vector-extension lane indices in the RTL. */
op[opc] =
GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc])));
}
goto constant_arg;
case SIMD_ARG_LANE_INDEX:
/* Must be a previous operand into which this is an index. */
gcc_assert (opc > 0);
......@@ -922,6 +939,7 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
/* Fall through - if the lane index isn't a constant then
the next case will error. */
case SIMD_ARG_CONSTANT:
constant_arg:
if (!(*insn_data[icode].operand[opc].predicate)
(op[opc], mode))
{
......@@ -1030,6 +1048,8 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
if (d->qualifiers[qualifiers_k] & qualifier_lane_index)
args[k] = SIMD_ARG_LANE_INDEX;
else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index)
args[k] = SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX;
else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
args[k] = SIMD_ARG_CONSTANT;
else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)
......@@ -1053,7 +1073,7 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
/* The interface to aarch64_simd_expand_args expects a 0 if
the function is void, and a 1 if it is not. */
return aarch64_simd_expand_args
(target, icode, !is_void, exp, &args[1]);
(target, icode, !is_void, exp, &args[1], d->mode);
}
rtx
......
gcc/config/aarch64/aarch64-simd-builtins.def
......@@ -88,9 +88,9 @@
BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0)
BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0)
/* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>. */
BUILTIN_VQ (LOADSTRUCT_LANE, ld2_lane, 0)
BUILTIN_VQ (LOADSTRUCT_LANE, ld3_lane, 0)
BUILTIN_VQ (LOADSTRUCT_LANE, ld4_lane, 0)
BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0)
BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0)
BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0)
/* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */
BUILTIN_VDC (STORESTRUCT, st2, 0)
BUILTIN_VDC (STORESTRUCT, st3, 0)
......@@ -100,9 +100,9 @@
BUILTIN_VQ (STORESTRUCT, st3, 0)
BUILTIN_VQ (STORESTRUCT, st4, 0)
BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0)
BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0)
BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0)
BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0)
BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0)
BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0)
BUILTIN_VQW (BINOP, saddl2, 0)
BUILTIN_VQW (BINOP, uaddl2, 0)
......
gcc/config/aarch64/aarch64-simd.md
......@@ -3919,10 +3919,13 @@
(unspec:OI [(match_operand:<V_TWO_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
(match_operand:OI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
UNSPEC_LD2_LANE))]
"TARGET_SIMD"
"ld2\\t{%S0.<Vetype> - %T0.<Vetype>}[%3], %1"
{
operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3])));
return "ld2\\t{%S0.<Vetype> - %T0.<Vetype>}[%3], %1";
}
[(set_attr "type" "neon_load2_one_lane")]
)
......@@ -3959,9 +3962,9 @@
(define_insn "vec_store_lanesoi_lane<mode>"
[(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_ST2_LANE))]
UNSPEC_ST2_LANE))]
"TARGET_SIMD"
{
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
......@@ -4014,10 +4017,13 @@
(unspec:CI [(match_operand:<V_THREE_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
(match_operand:CI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_LD3_LANE))]
"TARGET_SIMD"
"ld3\\t{%S0.<Vetype> - %U0.<Vetype>}[%3], %1"
{
operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3])));
return "ld3\\t{%S0.<Vetype> - %U0.<Vetype>}[%3], %1";
}
[(set_attr "type" "neon_load3_one_lane")]
)
......@@ -4054,9 +4060,9 @@
(define_insn "vec_store_lanesci_lane<mode>"
[(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_ST3_LANE))]
UNSPEC_ST3_LANE))]
"TARGET_SIMD"
{
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
......@@ -4109,10 +4115,13 @@
(unspec:XI [(match_operand:<V_FOUR_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
(match_operand:XI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_LD4_LANE))]
"TARGET_SIMD"
"ld4\\t{%S0.<Vetype> - %V0.<Vetype>}[%3], %1"
{
operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3])));
return "ld4\\t{%S0.<Vetype> - %V0.<Vetype>}[%3], %1";
}
[(set_attr "type" "neon_load4_one_lane")]
)
......@@ -4149,9 +4158,9 @@
(define_insn "vec_store_lanesxi_lane<mode>"
[(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_ST4_LANE))]
UNSPEC_ST4_LANE))]
"TARGET_SIMD"
{
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
......@@ -4566,14 +4575,12 @@
(match_operand:DI 1 "register_operand" "w")
(match_operand:OI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
machine_mode mode = <V_TWO_ELEM>mode;
rtx mem = gen_rtx_MEM (mode, operands[1]);
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
NULL);
emit_insn (gen_aarch64_vec_load_lanesoi_lane<mode> (operands[0],
mem,
operands[2],
......@@ -4586,14 +4593,12 @@
(match_operand:DI 1 "register_operand" "w")
(match_operand:CI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
machine_mode mode = <V_THREE_ELEM>mode;
rtx mem = gen_rtx_MEM (mode, operands[1]);
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
NULL);
emit_insn (gen_aarch64_vec_load_lanesci_lane<mode> (operands[0],
mem,
operands[2],
......@@ -4606,14 +4611,12 @@
(match_operand:DI 1 "register_operand" "w")
(match_operand:XI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
machine_mode mode = <V_FOUR_ELEM>mode;
rtx mem = gen_rtx_MEM (mode, operands[1]);
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
NULL);
emit_insn (gen_aarch64_vec_load_lanesxi_lane<mode> (operands[0],
mem,
operands[2],
......@@ -4850,54 +4853,45 @@
DONE;
})
(define_expand "aarch64_st2_lane<VQ:mode>"
(define_expand "aarch64_st2_lane<mode>"
[(match_operand:DI 0 "register_operand" "r")
(match_operand:OI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
machine_mode mode = <V_TWO_ELEM>mode;
rtx mem = gen_rtx_MEM (mode, operands[0]);
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
emit_insn (gen_vec_store_lanesoi_lane<VQ:mode> (mem,
operands[1],
operands[2]));
emit_insn (gen_vec_store_lanesoi_lane<mode> (mem, operands[1], operands[2]));
DONE;
})
(define_expand "aarch64_st3_lane<VQ:mode>"
(define_expand "aarch64_st3_lane<mode>"
[(match_operand:DI 0 "register_operand" "r")
(match_operand:CI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
machine_mode mode = <V_THREE_ELEM>mode;
rtx mem = gen_rtx_MEM (mode, operands[0]);
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
emit_insn (gen_vec_store_lanesci_lane<VQ:mode> (mem,
operands[1],
operands[2]));
emit_insn (gen_vec_store_lanesci_lane<mode> (mem, operands[1], operands[2]));
DONE;
})
(define_expand "aarch64_st4_lane<VQ:mode>"
(define_expand "aarch64_st4_lane<mode>"
[(match_operand:DI 0 "register_operand" "r")
(match_operand:XI 1 "register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
machine_mode mode = <V_FOUR_ELEM>mode;
rtx mem = gen_rtx_MEM (mode, operands[0]);
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
emit_insn (gen_vec_store_lanesxi_lane<VQ:mode> (mem,
operands[1],
operands[2]));
emit_insn (gen_vec_store_lanesxi_lane<mode> (mem, operands[1], operands[2]));
DONE;
})
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x2x2_t
f_vld2_lane_f32 (float32_t * p, float32x2x2_t v)
{
float32x2x2_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_f32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_f32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x1x2_t
f_vld2_lane_f64 (float64_t * p, float64x1x2_t v)
{
float64x1x2_t res;
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_f64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_f64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
poly8x8x2_t
f_vld2_lane_p8 (poly8_t * p, poly8x8x2_t v)
{
poly8x8x2_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_p8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_p8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x4x2_t
f_vld2_lane_s16 (int16_t * p, int16x4x2_t v)
{
int16x4x2_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_s16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_s16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x2x2_t
f_vld2_lane_s32 (int32_t * p, int32x2x2_t v)
{
int32x2x2_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_s32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_s32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x1x2_t
f_vld2_lane_s64 (int64_t * p, int64x1x2_t v)
{
int64x1x2_t res;
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_s64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_s64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int8x8x2_t
f_vld2_lane_s8 (int8_t * p, int8x8x2_t v)
{
int8x8x2_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_s8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_s8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x4x2_t
f_vld2_lane_u16 (uint16_t * p, uint16x4x2_t v)
{
uint16x4x2_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_u16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_u16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x2x2_t
f_vld2_lane_u32 (uint32_t * p, uint32x2x2_t v)
{
uint32x2x2_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_u32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_u32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x1x2_t
f_vld2_lane_u64 (uint64_t * p, uint64x1x2_t v)
{
uint64x1x2_t res;
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_u64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_u64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint8x8x2_t
f_vld2_lane_u8 (uint8_t * p, uint8x8x2_t v)
{
uint8x8x2_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_u8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2_lane_u8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x4x2_t
f_vld2q_lane_f32 (float32_t * p, float32x4x2_t v)
{
float32x4x2_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_f32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_f32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x2x2_t
f_vld2q_lane_f64 (float64_t * p, float64x2x2_t v)
{
float64x2x2_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_f64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_f64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
poly8x16x2_t
f_vld2q_lane_p8 (poly8_t * p, poly8x16x2_t v)
{
poly8x16x2_t res;
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_p8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_p8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x8x2_t
f_vld2q_lane_s16 (int16_t * p, int16x8x2_t v)
{
int16x8x2_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_s16 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_s16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x4x2_t
f_vld2q_lane_s32 (int32_t * p, int32x4x2_t v)
{
int32x4x2_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_s32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_s32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x2x2_t
f_vld2q_lane_s64 (int64_t * p, int64x2x2_t v)
{
int64x2x2_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_s64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_s64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int8x16x2_t
f_vld2q_lane_s8 (int8_t * p, int8x16x2_t v)
{
int8x16x2_t res;
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_s8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_s8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x8x2_t
f_vld2q_lane_u16 (uint16_t * p, uint16x8x2_t v)
{
uint16x8x2_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_u16 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_u16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x4x2_t
f_vld2q_lane_u32 (uint32_t * p, uint32x4x2_t v)
{
uint32x4x2_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_u32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_u32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x2x2_t
f_vld2q_lane_u64 (uint64_t * p, uint64x2x2_t v)
{
uint64x2x2_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_u64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_u64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint8x16x2_t
f_vld2q_lane_u8 (uint8_t * p, uint8x16x2_t v)
{
uint8x16x2_t res;
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_u8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld2q_lane_u8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x2x3_t
f_vld3_lane_f32 (float32_t * p, float32x2x3_t v)
{
float32x2x3_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_f32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_f32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x1x3_t
f_vld3_lane_f64 (float64_t * p, float64x1x3_t v)
{
float64x1x3_t res;
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_f64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_f64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
poly8x8x3_t
f_vld3_lane_p8 (poly8_t * p, poly8x8x3_t v)
{
poly8x8x3_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_p8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_p8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x4x3_t
f_vld3_lane_s16 (int16_t * p, int16x4x3_t v)
{
int16x4x3_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_s16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_s16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x2x3_t
f_vld3_lane_s32 (int32_t * p, int32x2x3_t v)
{
int32x2x3_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_s32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_s32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x1x3_t
f_vld3_lane_s64 (int64_t * p, int64x1x3_t v)
{
int64x1x3_t res;
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_s64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_s64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int8x8x3_t
f_vld3_lane_s8 (int8_t * p, int8x8x3_t v)
{
int8x8x3_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_s8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_s8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x4x3_t
f_vld3_lane_u16 (uint16_t * p, uint16x4x3_t v)
{
uint16x4x3_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_u16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_u16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x2x3_t
f_vld3_lane_u32 (uint32_t * p, uint32x2x3_t v)
{
uint32x2x3_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_u32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_u32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x1x3_t
f_vld3_lane_u64 (uint64_t * p, uint64x1x3_t v)
{
uint64x1x3_t res;
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_u64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_u64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint8x8x3_t
f_vld3_lane_u8 (uint8_t * p, uint8x8x3_t v)
{
uint8x8x3_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_u8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3_lane_u8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x4x3_t
f_vld3q_lane_f32 (float32_t * p, float32x4x3_t v)
{
float32x4x3_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_f32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_f32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x2x3_t
f_vld3q_lane_f64 (float64_t * p, float64x2x3_t v)
{
float64x2x3_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_f64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_f64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
poly8x16x3_t
f_vld3q_lane_p8 (poly8_t * p, poly8x16x3_t v)
{
poly8x16x3_t res;
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_p8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_p8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x8x3_t
f_vld3q_lane_s16 (int16_t * p, int16x8x3_t v)
{
int16x8x3_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_s16 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_s16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x4x3_t
f_vld3q_lane_s32 (int32_t * p, int32x4x3_t v)
{
int32x4x3_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_s32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_s32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x2x3_t
f_vld3q_lane_s64 (int64_t * p, int64x2x3_t v)
{
int64x2x3_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_s64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_s64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int8x16x3_t
f_vld3q_lane_s8 (int8_t * p, int8x16x3_t v)
{
int8x16x3_t res;
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_s8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_s8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x8x3_t
f_vld3q_lane_u16 (uint16_t * p, uint16x8x3_t v)
{
uint16x8x3_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_u16 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_u16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x4x3_t
f_vld3q_lane_u32 (uint32_t * p, uint32x4x3_t v)
{
uint32x4x3_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_u32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_u32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x2x3_t
f_vld3q_lane_u64 (uint64_t * p, uint64x2x3_t v)
{
uint64x2x3_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_u64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_u64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint8x16x3_t
f_vld3q_lane_u8 (uint8_t * p, uint8x16x3_t v)
{
uint8x16x3_t res;
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_u8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld3q_lane_u8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x2x4_t
f_vld4_lane_f32 (float32_t * p, float32x2x4_t v)
{
float32x2x4_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_f32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_f32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x1x4_t
f_vld4_lane_f64 (float64_t * p, float64x1x4_t v)
{
float64x1x4_t res;
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_f64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_f64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
poly8x8x4_t
f_vld4_lane_p8 (poly8_t * p, poly8x8x4_t v)
{
poly8x8x4_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_p8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_p8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x4x4_t
f_vld4_lane_s16 (int16_t * p, int16x4x4_t v)
{
int16x4x4_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_s16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_s16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x2x4_t
f_vld4_lane_s32 (int32_t * p, int32x2x4_t v)
{
int32x2x4_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_s32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_s32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x1x4_t
f_vld4_lane_s64 (int64_t * p, int64x1x4_t v)
{
int64x1x4_t res;
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_s64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_s64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int8x8x4_t
f_vld4_lane_s8 (int8_t * p, int8x8x4_t v)
{
int8x8x4_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_s8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_s8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x4x4_t
f_vld4_lane_u16 (uint16_t * p, uint16x4x4_t v)
{
uint16x4x4_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_u16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_u16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x2x4_t
f_vld4_lane_u32 (uint32_t * p, uint32x2x4_t v)
{
uint32x2x4_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_u32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_u32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x1x4_t
f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v)
{
uint64x1x4_t res;
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_u64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_u64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint8x8x4_t
f_vld4_lane_u8 (uint8_t * p, uint8x8x4_t v)
{
uint8x8x4_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_u8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4_lane_u8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x4x4_t
f_vld4q_lane_f32 (float32_t * p, float32x4x4_t v)
{
float32x4x4_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_f32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_f32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x2x4_t
f_vld4q_lane_f64 (float64_t * p, float64x2x4_t v)
{
float64x2x4_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_f64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_f64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
poly8x16x4_t
f_vld4q_lane_p8 (poly8_t * p, poly8x16x4_t v)
{
poly8x16x4_t res;
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_p8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_p8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x8x4_t
f_vld4q_lane_s16 (int16_t * p, int16x8x4_t v)
{
int16x8x4_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_s16 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_s16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x4x4_t
f_vld4q_lane_s32 (int32_t * p, int32x4x4_t v)
{
int32x4x4_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_s32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_s32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x2x4_t
f_vld4q_lane_s64 (int64_t * p, int64x2x4_t v)
{
int64x2x4_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_s64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_s64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int8x16x4_t
f_vld4q_lane_s8 (int8_t * p, int8x16x4_t v)
{
int8x16x4_t res;
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_s8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_s8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x8x4_t
f_vld4q_lane_u16 (uint16_t * p, uint16x8x4_t v)
{
uint16x8x4_t res;
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_u16 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_u16 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x4x4_t
f_vld4q_lane_u32 (uint32_t * p, uint32x4x4_t v)
{
uint32x4x4_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_u32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_u32 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x2x4_t
f_vld4q_lane_u64 (uint64_t * p, uint64x2x4_t v)
{
uint64x2x4_t res;
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_u64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_u64 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint8x16x4_t
f_vld4q_lane_u8 (uint8_t * p, uint8x16x4_t v)
{
uint8x16x4_t res;
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_u8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
res = vld4q_lane_u8 (p, v, -1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_f32 (float32_t * p, float32x2x2_t v)
{
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2_lane_f32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2_lane_f32 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2_lane_f64 (float64_t * p, float64x1x2_t v)
{
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst2_lane_f64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst2_lane_f64 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_p8 (poly8_t * p, poly8x8x2_t v)
{
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2_lane_p8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2_lane_p8 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_s16 (int16_t * p, int16x4x2_t v)
{
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2_lane_s16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2_lane_s16 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_s32 (int32_t * p, int32x2x2_t v)
{
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2_lane_s32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2_lane_s32 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2_lane_s64 (int64_t * p, int64x1x2_t v)
{
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst2_lane_s64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst2_lane_s64 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_s8 (int8_t * p, int8x8x2_t v)
{
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2_lane_s8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2_lane_s8 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_u16 (uint16_t * p, uint16x4x2_t v)
{
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2_lane_u16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2_lane_u16 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_u32 (uint32_t * p, uint32x2x2_t v)
{
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2_lane_u32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2_lane_u32 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2_lane_u64 (uint64_t * p, uint64x1x2_t v)
{
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst2_lane_u64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst2_lane_u64 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_u8 (uint8_t * p, uint8x8x2_t v)
{
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2_lane_u8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2_lane_u8 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_f32 (float32_t * p, float32x4x2_t v)
{
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2q_lane_f32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2q_lane_f32 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_f64 (float64_t * p, float64x2x2_t v)
{
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2q_lane_f64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2q_lane_f64 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_p8 (poly8_t * p, poly8x16x2_t v)
{
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
vst2q_lane_p8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
vst2q_lane_p8 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_s16 (int16_t * p, int16x8x2_t v)
{
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2q_lane_s16 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2q_lane_s16 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_s32 (int32_t * p, int32x4x2_t v)
{
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2q_lane_s32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2q_lane_s32 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_s64 (int64_t * p, int64x2x2_t v)
{
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2q_lane_s64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2q_lane_s64 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_s8 (int8_t * p, int8x16x2_t v)
{
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
vst2q_lane_s8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
vst2q_lane_s8 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_u16 (uint16_t * p, uint16x8x2_t v)
{
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2q_lane_u16 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst2q_lane_u16 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_u32 (uint32_t * p, uint32x4x2_t v)
{
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2q_lane_u32 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst2q_lane_u32 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_u64 (uint64_t * p, uint64x2x2_t v)
{
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2q_lane_u64 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst2q_lane_u64 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_u8 (uint8_t * p, uint8x16x2_t v)
{
/* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
vst2q_lane_u8 (p, v, 16);
/* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
vst2q_lane_u8 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_f32 (float32_t * p, float32x2x3_t v)
{
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst3_lane_f32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst3_lane_f32 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3_lane_f64 (float64_t * p, float64x1x3_t v)
{
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst3_lane_f64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst3_lane_f64 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_p8 (poly8_t * p, poly8x8x3_t v)
{
/* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst3_lane_p8 (p, v, 8);
/* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
vst3_lane_p8 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_s16 (int16_t * p, int16x4x3_t v)
{
/* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst3_lane_s16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
vst3_lane_s16 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_s32 (int32_t * p, int32x2x3_t v)
{
/* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst3_lane_s32 (p, v, 2);
/* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
vst3_lane_s32 (p, v, -1);
return;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3_lane_s64 (int64_t * p, int64x1x3_t v)
{
/* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst3_lane_s64 (p, v, 1);
/* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
vst3_lane_s64 (p, v, -1);
return;
}
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