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riscv-gcc-1
Commit 4bf02aaf by Uros Bizjak
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i386.md (simple LEA peephole2s): Add zero-extend variants of PLUS and MULT simple LEA patterns. 

	* config/i386/i386.md (simple LEA peephole2s): Add zero-extend
	variants of PLUS and MULT simple LEA patterns.  Disable PLUS
	patterns for TARGET_OPT_AGU.

From-SVN: r190301
parent 04f92ff4
Showing with 130 additions and 36 deletions
gcc/ChangeLog
2012-08-10 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (simple LEA peephole2s): Add zero-extend
variants of PLUS and MULT simple LEA patterns. Disable PLUS
patterns for TARGET_OPT_AGU.
2012-08-10 Richard Guenther <rguenther@suse.de>
* Makefile.in (OBJS): Remove matrix-reorg.o.
......@@ -124,8 +130,8 @@
2012-08-10 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/i386.c (ix86_init_mmx_sse_builtins): Fix builtin
target mask of __builtin_ia32_rdseed_di_step.
* config/i386/i386.c (ix86_init_mmx_sse_builtins): Fix
target mask of __builtin_ia32_rdseed_di_step builtin.
2012-08-10 Richard Guenther <rguenther@suse.de>
......@@ -377,10 +383,10 @@
2012-08-09 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/alpha.c (alpha_pad_noreturn): Rename to ...
(alpha_pad_function_end): ... this. Also insert NOP between
sibling call and GP load.
(alpha_reorg): Update call to alpha_pad_function_end. Expand comment.
* config/alpha/alpha.c (alpha_pad_noreturn): Rename to ...
(alpha_pad_function_end): ... this. Also insert NOP between
sibling call and GP load.
(alpha_reorg): Update call to alpha_pad_function_end. Expand comment.
2012-08-09 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
......@@ -1843,25 +1849,25 @@
2012-07-27 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md: Delete "q" constraint.
* config/rs6000/dfp.md (movsd_hardfloat, movsd_softfloat):
Delete the "q" alternative.
* config/rs6000/predicates.md (gpc_reg_operand): Adjust.
* config/rs6000/rs6000.c (rs6000_debug_reg_global,
rs6000_init_hard_regno_mode_ok, rs6000_dbx_register_number):
Adjust to MQ_REGNO removal.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Adjust
comment.
(REG_ALLOC_ORDER): Adjust comment. Remove MQ from alloc order.
(enum reg_class): Adjust comment. Delete MQ_REGS.
(REG_CLASS_CONTENTS): Adjust.
(REGISTER_NAMES, ADDITIONAL_REGISTER_NAMES): Adjust comment.
* config/rs6000/rs6000.md: Delete MQ_REGNO.
(movsi_internal1, movsi_internal1_single, movhi_internal,
movqi_internal, movcc_internal1, movsf_hardfloat,
movsf_softfloat): Delete the "q" alternative.
(ctr<mode>_internal1, ctr<mode>_internal2, ctr<mode>_internal5,
ctr<mode>_internal6): Delete "q" constraint.
* config/rs6000/constraints.md: Delete "q" constraint.
* config/rs6000/dfp.md (movsd_hardfloat, movsd_softfloat):
Delete the "q" alternative.
* config/rs6000/predicates.md (gpc_reg_operand): Adjust.
* config/rs6000/rs6000.c (rs6000_debug_reg_global)
(rs6000_init_hard_regno_mode_ok, rs6000_dbx_register_number):
adjust to MQ_REGNO removal.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Adjust
comment.
(REG_ALLOC_ORDER): Adjust comment. Remove MQ from alloc order.
(enum reg_class): Adjust comment. Delete MQ_REGS.
(REG_CLASS_CONTENTS): Adjust.
(REGISTER_NAMES, ADDITIONAL_REGISTER_NAMES): Adjust comment.
* config/rs6000/rs6000.md: Delete MQ_REGNO.
(movsi_internal1, movsi_internal1_single, movhi_internal,
movqi_internal, movcc_internal1, movsf_hardfloat,
movsf_softfloat): Delete the "q" alternative.
(ctr<mode>_internal1, ctr<mode>_internal2, ctr<mode>_internal5,
ctr<mode>_internal6): Delete "q" constraint.
2012-07-27 Richard Guenther <rguenther@suse.de>
......
gcc/config/i386/i386.md
......@@ -17317,12 +17317,15 @@
;; Attempt to convert simple lea to add/shift.
;; These can be created by move expanders.
;; Disable PLUS peepholes on TARGET_OPT_AGU, since all
;; relevant lea instructions were already split.
(define_peephole2
[(set (match_operand:SWI48 0 "register_operand")
(plus:SWI48 (match_dup 0)
(match_operand:SWI48 1 "<nonmemory_operand>")))]
"peep2_regno_dead_p (0, FLAGS_REG)"
"!TARGET_OPT_AGU
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])])
......@@ -17330,7 +17333,8 @@
[(set (match_operand:SWI48 0 "register_operand")
(plus:SWI48 (match_operand:SWI48 1 "<nonmemory_operand>")
(match_dup 0)))]
"peep2_regno_dead_p (0, FLAGS_REG)"
"!TARGET_OPT_AGU
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])])
......@@ -17338,9 +17342,9 @@
[(set (match_operand:SI 0 "register_operand")
(subreg:SI (plus:DI (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "nonmemory_operand")) 0))]
"TARGET_64BIT
&& peep2_regno_dead_p (0, FLAGS_REG)
&& REGNO (operands[0]) == REGNO (operands[1])"
"TARGET_64BIT && !TARGET_OPT_AGU
&& REGNO (operands[0]) == REGNO (operands[1])
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"operands[2] = gen_lowpart (SImode, operands[2]);")
......@@ -17349,27 +17353,81 @@
[(set (match_operand:SI 0 "register_operand")
(subreg:SI (plus:DI (match_operand:DI 1 "nonmemory_operand")
(match_operand:DI 2 "register_operand")) 0))]
"TARGET_64BIT
&& peep2_regno_dead_p (0, FLAGS_REG)
&& REGNO (operands[0]) == REGNO (operands[2])"
"TARGET_64BIT && !TARGET_OPT_AGU
&& REGNO (operands[0]) == REGNO (operands[2])
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])]
"operands[1] = gen_lowpart (SImode, operands[1]);")
(define_peephole2
[(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
(plus:SI (match_operand:SI 1 "register_operand")
(match_operand:SI 2 "nonmemory_operand"))))]
"TARGET_64BIT && !TARGET_OPT_AGU
&& REGNO (operands[0]) == REGNO (operands[1])
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0)
(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))
(clobber (reg:CC FLAGS_REG))])])
(define_peephole2
[(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
(plus:SI (match_operand:SI 1 "nonmemory_operand")
(match_operand:SI 2 "register_operand"))))]
"TARGET_64BIT && !TARGET_OPT_AGU
&& REGNO (operands[0]) == REGNO (operands[2])
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0)
(zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
(clobber (reg:CC FLAGS_REG))])])
(define_peephole2
[(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
(subreg:SI (plus:DI (match_dup 0)
(match_operand:DI 1 "nonmemory_operand")) 0)))]
"TARGET_64BIT && !TARGET_OPT_AGU
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0)
(zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
(clobber (reg:CC FLAGS_REG))])]
{
operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_lowpart (SImode, operands[0]);
})
(define_peephole2
[(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
(subreg:SI (plus:DI (match_operand:DI 1 "nonmemory_operand")
(match_dup 0)) 0)))]
"TARGET_64BIT && !TARGET_OPT_AGU
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0)
(zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
(clobber (reg:CC FLAGS_REG))])]
{
operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_lowpart (SImode, operands[0]);
})
(define_peephole2
[(set (match_operand:SWI48 0 "register_operand")
(mult:SWI48 (match_dup 0)
(match_operand:SWI48 1 "const_int_operand")))]
"exact_log2 (INTVAL (operands[1])) >= 0
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 2)))
[(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])]
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
"operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
(define_peephole2
[(set (match_operand:SI 0 "register_operand")
(subreg:SI (mult:DI (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "const_int_operand")) 0))]
(match_operand:DI 2 "const_int_operand")) 0))]
"TARGET_64BIT
&& exact_log2 (INTVAL (operands[2])) >= 0
&& REGNO (operands[0]) == REGNO (operands[1])
......@@ -17378,6 +17436,36 @@
(clobber (reg:CC FLAGS_REG))])]
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
(define_peephole2
[(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
(mult:SI (match_operand:SI 1 "register_operand")
(match_operand:SI 2 "const_int_operand"))))]
"TARGET_64BIT
&& exact_log2 (INTVAL (operands[2])) >= 0
&& REGNO (operands[0]) == REGNO (operands[1])
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0)
(zero_extend (ashift:SI (match_dup 1) (match_dup 2))))
(clobber (reg:CC FLAGS_REG))])]
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
(define_peephole2
[(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
(subreg:SI (mult:DI (match_dup 0)
(match_operand:DI 1 "const_int_operand")) 0)))]
"TARGET_64BIT
&& exact_log2 (INTVAL (operands[2])) >= 0
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0)
(zero_extend:DI (ashift:SI (match_dup 2) (match_dup 1))))
(clobber (reg:CC FLAGS_REG))])]
{
operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
operands[2] = gen_lowpart (SImode, operands[0]);
})
;; The ESP adjustments can be done by the push and pop instructions. Resulting
;; code is shorter, since push is only 1 byte, while add imm, %esp is 3 bytes.
;; On many CPUs it is also faster, since special hardware to avoid esp
......
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