Skip to content

R
riscv-gcc-1
Commit 4bc63138 by Jiong Wang Committed by Jiong Wang
Options

[3/4] ARMv8.2-A testsuite for new vector intrinsics 

gcc/testsuite/

	* gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c: New.

From-SVN: r240923
parent 8f3edb07
Showing with 1145 additions and 0 deletions
gcc/testsuite/ChangeLog
2016-10-10 Jiong Wang <jiong.wang@arm.com> 2016-10-10 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c: New.
2016-10-10 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (FP16_SUPPORTED): * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (FP16_SUPPORTED):
Enable AArch64. Enable AArch64.
* gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Add support for * gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Add support for
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A FP16_C (13.4)
#define B FP16_C (-56.8)
#define C FP16_C (-34.8)
#define D FP16_C (12)
#define E FP16_C (63.1)
#define F FP16_C (19.1)
#define G FP16_C (-4.8)
#define H FP16_C (77)
#define I FP16_C (0.7)
#define J FP16_C (-78)
#define K FP16_C (11.23)
#define L FP16_C (98)
#define M FP16_C (87.1)
#define N FP16_C (-8)
#define O FP16_C (-1.1)
#define P FP16_C (-9.7)
/* Expected results for vdiv. */
VECT_VAR_DECL (expected_div_static, hfloat, 16, 4) []
= { 0x32CC /* A / E. */, 0xC1F3 /* B / F. */,
0x4740 /* C / G. */, 0x30FD /* D / H. */ };
VECT_VAR_DECL (expected_div_static, hfloat, 16, 8) []
= { 0x32CC /* A / E. */, 0xC1F3 /* B / F. */,
0x4740 /* C / G. */, 0x30FD /* D / H. */,
0x201D /* I / M. */, 0x48E0 /* J / N. */,
0xC91B /* K / O. */, 0xC90D /* L / P. */ };
void exec_vdiv_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VDIV (FP16)"
clean_results ();
DECL_VARIABLE(vsrc_1, float, 16, 4);
DECL_VARIABLE(vsrc_2, float, 16, 4);
VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
DECL_VARIABLE (vector_res, float, 16, 4)
= vdiv_f16 (VECT_VAR (vsrc_1, float, 16, 4),
VECT_VAR (vsrc_2, float, 16, 4));
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_div_static, "");
#undef TEST_MSG
#define TEST_MSG "VDIVQ (FP16)"
clean_results ();
DECL_VARIABLE(vsrc_1, float, 16, 8);
DECL_VARIABLE(vsrc_2, float, 16, 8);
VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
DECL_VARIABLE (vector_res, float, 16, 8)
= vdivq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
VECT_VAR (vsrc_2, float, 16, 8));
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_div_static, "");
}
int
main (void)
{
exec_vdiv_f16 ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A0 FP16_C (34.8)
#define B0 FP16_C (__builtin_nanf (""))
#define C0 FP16_C (-__builtin_nanf (""))
#define D0 FP16_C (0.0)
#define A1 FP16_C (1025.8)
#define B1 FP16_C (13.4)
#define C1 FP16_C (__builtin_nanf (""))
#define D1 FP16_C (10)
#define E1 FP16_C (-0.0)
#define F1 FP16_C (-__builtin_nanf (""))
#define G1 FP16_C (0.0)
#define H1 FP16_C (10)
/* Expected results for vmaxnmv. */
uint16_t expect = 0x505A /* A0. */;
uint16_t expect_alt = 0x6402 /* A1. */;
void exec_vmaxnmv_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VMAXNMV (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 4);
VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
VLOAD (vsrc, buf_src, , float, f, 16, 4);
float16_t vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
VLOAD (vsrc, buf_src1, , float, f, 16, 4);
vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
VLOAD (vsrc, buf_src2, , float, f, 16, 4);
vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
VLOAD (vsrc, buf_src3, , float, f, 16, 4);
vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
#undef TEST_MSG
#define TEST_MSG "VMAXNMVQ (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 8);
VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src, q, float, f, 16, 8);
vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
}
int
main (void)
{
exec_vmaxnmv_f16 ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A0 FP16_C (123.4)
#define B0 FP16_C (-567.8)
#define C0 FP16_C (34.8)
#define D0 FP16_C (0.0)
#define A1 FP16_C (1025.8)
#define B1 FP16_C (13.4)
#define C1 FP16_C (-567.8)
#define D1 FP16_C (10)
#define E1 FP16_C (-0.0)
#define F1 FP16_C (567.8)
#define G1 FP16_C (0.0)
#define H1 FP16_C (10)
/* Expected results for vmaxv. */
uint16_t expect = 0x57B6 /* A0. */;
uint16_t expect_alt = 0x6402 /* A1. */;
void exec_vmaxv_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VMAXV (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 4);
VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
VLOAD (vsrc, buf_src, , float, f, 16, 4);
float16_t vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
VLOAD (vsrc, buf_src1, , float, f, 16, 4);
vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
VLOAD (vsrc, buf_src2, , float, f, 16, 4);
vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
VLOAD (vsrc, buf_src3, , float, f, 16, 4);
vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
#undef TEST_MSG
#define TEST_MSG "VMAXVQ (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 8);
VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src, q, float, f, 16, 8);
vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
}
int
main (void)
{
exec_vmaxv_f16 ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A0 FP16_C (-567.8)
#define B0 FP16_C (__builtin_nanf (""))
#define C0 FP16_C (34.8)
#define D0 FP16_C (-__builtin_nanf (""))
#define A1 FP16_C (-567.8)
#define B1 FP16_C (1025.8)
#define C1 FP16_C (-__builtin_nanf (""))
#define D1 FP16_C (10)
#define E1 FP16_C (-0.0)
#define F1 FP16_C (__builtin_nanf (""))
#define G1 FP16_C (0.0)
#define H1 FP16_C (10)
/* Expected results for vminnmv. */
uint16_t expect = 0xE070 /* A0. */;
uint16_t expect_alt = 0xE070 /* A1. */;
void exec_vminnmv_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VMINNMV (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 4);
VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
VLOAD (vsrc, buf_src, , float, f, 16, 4);
float16_t vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
VLOAD (vsrc, buf_src1, , float, f, 16, 4);
vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
VLOAD (vsrc, buf_src2, , float, f, 16, 4);
vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
VLOAD (vsrc, buf_src3, , float, f, 16, 4);
vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
#undef TEST_MSG
#define TEST_MSG "VMINNMVQ (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 8);
VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src, q, float, f, 16, 8);
vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
}
int
main (void)
{
exec_vminnmv_f16 ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A0 FP16_C (-567.8)
#define B0 FP16_C (123.4)
#define C0 FP16_C (34.8)
#define D0 FP16_C (0.0)
#define A1 FP16_C (-567.8)
#define B1 FP16_C (1025.8)
#define C1 FP16_C (13.4)
#define D1 FP16_C (10)
#define E1 FP16_C (-0.0)
#define F1 FP16_C (567.8)
#define G1 FP16_C (0.0)
#define H1 FP16_C (10)
/* Expected results for vminv. */
uint16_t expect = 0xE070 /* A0. */;
uint16_t expect_alt = 0xE070 /* A1. */;
void exec_vminv_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VMINV (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 4);
VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
VLOAD (vsrc, buf_src, , float, f, 16, 4);
float16_t vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
VLOAD (vsrc, buf_src1, , float, f, 16, 4);
vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
VLOAD (vsrc, buf_src2, , float, f, 16, 4);
vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
VLOAD (vsrc, buf_src3, , float, f, 16, 4);
vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
if (* (uint16_t *) &vector_res != expect)
abort ();
#undef TEST_MSG
#define TEST_MSG "VMINVQ (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 8);
VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src, q, float, f, 16, 8);
vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
if (* (uint16_t *) &vector_res != expect_alt)
abort ();
}
int
main (void)
{
exec_vminv_f16 ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A FP16_C (13.4)
#define B FP16_C (__builtin_inff ())
#define C FP16_C (-34.8)
#define D FP16_C (-__builtin_inff ())
#define E FP16_C (63.1)
#define F FP16_C (0.0)
#define G FP16_C (-4.8)
#define H FP16_C (0.0)
#define I FP16_C (0.7)
#define J FP16_C (-__builtin_inff ())
#define K FP16_C (11.23)
#define L FP16_C (98)
#define M FP16_C (87.1)
#define N FP16_C (-0.0)
#define O FP16_C (-1.1)
#define P FP16_C (7)
/* Expected results for vmulx. */
VECT_VAR_DECL (expected_static, hfloat, 16, 4) []
= { 0x629B /* A * E. */, 0x4000 /* FP16_C (2.0f). */,
0x5939 /* C * G. */, 0xC000 /* FP16_C (-2.0f). */ };
VECT_VAR_DECL (expected_static, hfloat, 16, 8) []
= { 0x629B /* A * E. */, 0x4000 /* FP16_C (2.0f). */,
0x5939 /* C * G. */, 0xC000 /* FP16_C (-2.0f). */,
0x53A0 /* I * M. */, 0x4000 /* FP16_C (2.0f). */,
0xCA2C /* K * O. */, 0x615C /* L * P. */ };
void exec_vmulx_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VMULX (FP16)"
clean_results ();
DECL_VARIABLE(vsrc_1, float, 16, 4);
DECL_VARIABLE(vsrc_2, float, 16, 4);
VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
DECL_VARIABLE (vector_res, float, 16, 4)
= vmulx_f16 (VECT_VAR (vsrc_1, float, 16, 4),
VECT_VAR (vsrc_2, float, 16, 4));
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_static, "");
#undef TEST_MSG
#define TEST_MSG "VMULXQ (FP16)"
clean_results ();
DECL_VARIABLE(vsrc_1, float, 16, 8);
DECL_VARIABLE(vsrc_2, float, 16, 8);
VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
DECL_VARIABLE (vector_res, float, 16, 8)
= vmulxq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
VECT_VAR (vsrc_2, float, 16, 8));
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_static, "");
}
int
main (void)
{
exec_vmulx_f16 ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A FP16_C (13.4)
#define B FP16_C (__builtin_inff ())
#define C FP16_C (-34.8)
#define D FP16_C (-__builtin_inff ())
#define E FP16_C (-0.0)
#define F FP16_C (19.1)
#define G FP16_C (-4.8)
#define H FP16_C (0.0)
float16_t elemE = E;
float16_t elemF = F;
float16_t elemG = G;
float16_t elemH = H;
#define I FP16_C (0.7)
#define J FP16_C (-78)
#define K FP16_C (11.23)
#define L FP16_C (98)
#define M FP16_C (87.1)
#define N FP16_C (-8)
#define O FP16_C (-1.1)
#define P FP16_C (-9.7)
/* Expected results for vmulx_n. */
VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
= { 0x8000 /* A * E. */,
0xC000 /* FP16_C (-2.0f). */,
0x0000 /* C * E. */,
0x4000 /* FP16_C (2.0f). */ };
VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
= { 0x5BFF /* A * F. */,
0x7C00 /* B * F. */,
0xE131 /* C * F. */,
0xFC00 /* D * F. */ };
VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
= { 0xD405 /* A * G. */,
0xFC00 /* B * G. */,
0x5939 /* C * G. */,
0x7C00 /* D * G. */ };
VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
= { 0x0000 /* A * H. */,
0x4000 /* FP16_C (2.0f). */,
0x8000 /* C * H. */,
0xC000 /* FP16_C (-2.0f). */ };
VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
= { 0x8000 /* A * E. */,
0xC000 /* FP16_C (-2.0f). */,
0x0000 /* C * E. */,
0x4000 /* FP16_C (2.0f). */,
0x8000 /* I * E. */,
0x0000 /* J * E. */,
0x8000 /* K * E. */,
0x8000 /* L * E. */ };
VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
= { 0x5BFF /* A * F. */,
0x7C00 /* B * F. */,
0xE131 /* C * F. */,
0xFC00 /* D * F. */,
0x4AAF /* I * F. */,
0xE5D1 /* J * F. */,
0x5AB3 /* K * F. */,
0x674F /* L * F. */ };
VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
= { 0xD405 /* A * G. */,
0xFC00 /* B * G. */,
0x5939 /* C * G. */,
0x7C00 /* D * G. */,
0xC2B9 /* I * G. */,
0x5DDA /* J * G. */,
0xD2BD /* K * G. */,
0xDF5A /* L * G. */ };
VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
= { 0x0000 /* A * H. */,
0x4000 /* FP16_C (2.0f). */,
0x8000 /* C * H. */,
0xC000 /* FP16_C (-2.0f). */,
0x0000 /* I * H. */,
0x8000 /* J * H. */,
0x0000 /* K * H. */,
0x0000 /* L * H. */ };
void exec_vmulx_n_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VMULX_N (FP16)"
clean_results ();
DECL_VARIABLE (vsrc_1, float, 16, 4);
VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
DECL_VARIABLE (vector_res, float, 16, 4)
= vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemE);
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
VECT_VAR (vector_res, float, 16, 4)
= vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemF);
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
VECT_VAR (vector_res, float, 16, 4)
= vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemG);
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
VECT_VAR (vector_res, float, 16, 4)
= vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemH);
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
#undef TEST_MSG
#define TEST_MSG "VMULXQ_N (FP16)"
clean_results ();
DECL_VARIABLE (vsrc_1, float, 16, 8);
VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
DECL_VARIABLE (vector_res, float, 16, 8)
= vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemE);
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
VECT_VAR (vector_res, float, 16, 8)
= vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemF);
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
VECT_VAR (vector_res, float, 16, 8)
= vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemG);
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
VECT_VAR (vector_res, float, 16, 8)
= vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemH);
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
}
int
main (void)
{
exec_vmulx_n_f16 ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A FP16_C (123.4)
#define B FP16_C (__builtin_nanf ("")) /* NaN */
#define C FP16_C (-34.8)
#define D FP16_C (1024)
#define E FP16_C (663.1)
#define F FP16_C (169.1)
#define G FP16_C (-4.8)
#define H FP16_C (-__builtin_nanf ("")) /* NaN */
#define I FP16_C (0.7)
#define J FP16_C (-78)
#define K FP16_C (101.23)
#define L FP16_C (-1098)
#define M FP16_C (870.1)
#define N FP16_C (-8781)
#define O FP16_C (__builtin_inff ()) /* +Inf */
#define P FP16_C (-__builtin_inff ()) /* -Inf */
/* Expected results for vpminnm. */
VECT_VAR_DECL (expected_min_static, hfloat, 16, 4) []
= { 0x57B6 /* A. */, 0xD05A /* C. */, 0x5949 /* F. */, 0xC4CD /* G. */ };
VECT_VAR_DECL (expected_min_static, hfloat, 16, 8) []
= { 0x57B6 /* A. */, 0xD05A /* C. */, 0xD4E0 /* J. */, 0xE44A /* L. */,
0x5949 /* F. */, 0xC4CD /* G. */, 0xF04A /* N. */, 0xFC00 /* P. */ };
/* expected_max results for vpmaxnm. */
VECT_VAR_DECL (expected_max_static, hfloat, 16, 4) []
= { 0x57B6 /* A. */, 0x6400 /* D. */, 0x612E /* E. */, 0xC4CD /* G. */ };
VECT_VAR_DECL (expected_max_static, hfloat, 16, 8) []
= { 0x57B6 /* A. */, 0x6400 /* D. */, 0x399A /* I. */, 0x5654 /* K. */,
0x612E /* E. */, 0xC4CD /* G. */, 0x62CC /* M. */, 0x7C00 /* O. */ };
void exec_vpminmaxnm_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VPMINNM (FP16)"
clean_results ();
DECL_VARIABLE(vsrc_1, float, 16, 4);
DECL_VARIABLE(vsrc_2, float, 16, 4);
VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
DECL_VARIABLE (vector_res, float, 16, 4)
= vpminnm_f16 (VECT_VAR (vsrc_1, float, 16, 4),
VECT_VAR (vsrc_2, float, 16, 4));
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_min_static, "");
#undef TEST_MSG
#define TEST_MSG "VPMINNMQ (FP16)"
clean_results ();
DECL_VARIABLE(vsrc_1, float, 16, 8);
DECL_VARIABLE(vsrc_2, float, 16, 8);
VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
DECL_VARIABLE (vector_res, float, 16, 8)
= vpminnmq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
VECT_VAR (vsrc_2, float, 16, 8));
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_min_static, "");
#undef TEST_MSG
#define TEST_MSG "VPMAXNM (FP16)"
clean_results ();
VECT_VAR (vector_res, float, 16, 4)
= vpmaxnm_f16 (VECT_VAR (vsrc_1, float, 16, 4),
VECT_VAR (vsrc_2, float, 16, 4));
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_max_static, "");
#undef TEST_MSG
#define TEST_MSG "VPMAXNMQ (FP16)"
clean_results ();
VECT_VAR (vector_res, float, 16, 8)
= vpmaxnmq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
VECT_VAR (vsrc_2, float, 16, 8));
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_max_static, "");
}
int
main (void)
{
exec_vpminmaxnm_f16 ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A FP16_C (123.4)
#define RNDI_A 0x57B0 /* FP16_C (123). */
#define B FP16_C (-567.5)
#define RNDI_B 0xE070 /* FP16_C (-568). */
#define C FP16_C (-34.8)
#define RNDI_C 0xD060 /* FP16_C (-35). */
#define D FP16_C (1024)
#define RNDI_D 0x6400 /* FP16_C (1024). */
#define E FP16_C (663.1)
#define RNDI_E 0x612E /* FP16_C (663). */
#define F FP16_C (169.1)
#define RNDI_F 0x5948 /* FP16_C (169). */
#define G FP16_C (-4.8)
#define RNDI_G 0xC500 /* FP16_C (-5). */
#define H FP16_C (77.5)
#define RNDI_H 0x54E0 /* FP16_C (78). */
/* Expected results for vrndi. */
VECT_VAR_DECL (expected_static, hfloat, 16, 4) []
= { RNDI_A, RNDI_B, RNDI_C, RNDI_D };
VECT_VAR_DECL (expected_static, hfloat, 16, 8) []
= { RNDI_A, RNDI_B, RNDI_C, RNDI_D, RNDI_E, RNDI_F, RNDI_G, RNDI_H };
void exec_vrndi_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VRNDI (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 4);
VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A, B, C, D};
VLOAD (vsrc, buf_src, , float, f, 16, 4);
DECL_VARIABLE (vector_res, float, 16, 4)
= vrndi_f16 (VECT_VAR (vsrc, float, 16, 4));
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_static, "");
#undef TEST_MSG
#define TEST_MSG "VRNDIQ (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 8);
VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A, B, C, D, E, F, G, H};
VLOAD (vsrc, buf_src, q, float, f, 16, 8);
DECL_VARIABLE (vector_res, float, 16, 8)
= vrndiq_f16 (VECT_VAR (vsrc, float, 16, 8));
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_static, "");
}
int
main (void)
{
exec_vrndi_f16 ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c 0 → 100644
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
/* { dg-add-options arm_v8_2a_fp16_neon } */
/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define FP16_C(a) ((__fp16) a)
#define A FP16_C (123.4)
#define B FP16_C (567.8)
#define C FP16_C (34.8)
#define D FP16_C (1024)
#define E FP16_C (663.1)
#define F FP16_C (144.0)
#define G FP16_C (4.8)
#define H FP16_C (77)
#define SQRT_A 0x498E /* FP16_C (__builtin_sqrtf (123.4)). */
#define SQRT_B 0x4DF5 /* FP16_C (__builtin_sqrtf (567.8)). */
#define SQRT_C 0x45E6 /* FP16_C (__builtin_sqrtf (34.8)). */
#define SQRT_D 0x5000 /* FP16_C (__builtin_sqrtf (1024)). */
#define SQRT_E 0x4E70 /* FP16_C (__builtin_sqrtf (663.1)). */
#define SQRT_F 0x4A00 /* FP16_C (__builtin_sqrtf (144.0)). */
#define SQRT_G 0x4062 /* FP16_C (__builtin_sqrtf (4.8)). */
#define SQRT_H 0x4863 /* FP16_C (__builtin_sqrtf (77)). */
/* Expected results for vsqrt. */
VECT_VAR_DECL (expected_static, hfloat, 16, 4) []
= { SQRT_A, SQRT_B, SQRT_C, SQRT_D };
VECT_VAR_DECL (expected_static, hfloat, 16, 8) []
= { SQRT_A, SQRT_B, SQRT_C, SQRT_D, SQRT_E, SQRT_F, SQRT_G, SQRT_H };
void exec_vsqrt_f16 (void)
{
#undef TEST_MSG
#define TEST_MSG "VSQRT (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 4);
VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A, B, C, D};
VLOAD (vsrc, buf_src, , float, f, 16, 4);
DECL_VARIABLE (vector_res, float, 16, 4)
= vsqrt_f16 (VECT_VAR (vsrc, float, 16, 4));
vst1_f16 (VECT_VAR (result, float, 16, 4),
VECT_VAR (vector_res, float, 16, 4));
CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_static, "");
#undef TEST_MSG
#define TEST_MSG "VSQRTQ (FP16)"
clean_results ();
DECL_VARIABLE(vsrc, float, 16, 8);
VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A, B, C, D, E, F, G, H};
VLOAD (vsrc, buf_src, q, float, f, 16, 8);
DECL_VARIABLE (vector_res, float, 16, 8)
= vsqrtq_f16 (VECT_VAR (vsrc, float, 16, 8));
vst1q_f16 (VECT_VAR (result, float, 16, 8),
VECT_VAR (vector_res, float, 16, 8));
CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_static, "");
}
int
main (void)
{
exec_vsqrt_f16 ();
return 0;
}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment