sel-sched: correct reset of reset_sched_cycles_p (PR 85412)

2019-04-01  Andrey Belevantsev  <abel@ispras.ru>

	PR rtl-optimization/85412
	* sel-sched.c (sel_sched_region): Assign reset_sched_cycles_p before
	sel_sched_region_1, not after.

	* gcc.dg/pr85412.c: New test.

From-SVN: r270065

gcc/ChangeLog

 2019-04-01  Andrey Belevantsev  <abel@ispras.ru>
 
+	PR rtl-optimization/85412
+	* sel-sched.c (sel_sched_region): Assign reset_sched_cycles_p before
+	sel_sched_region_1, not after.
+
+2019-04-01  Andrey Belevantsev  <abel@ispras.ru>
+
 	PR rtl-optimization/86928
 	* sel-sched-ir.c (sel_redirect_edge_and_branch_force): Invoke
 	compute_live if necessary.

gcc/sel-sched.c

@@ -7650,11 +7650,11 @@ sel_sched_region (int rgn)
       /* Schedule always selecting the next insn to make the correct data
 	 for bundling or other later passes.  */
       pipelining_p = false;
+      reset_sched_cycles_p = false;
       force_next_insn = 1;
       sel_sched_region_1 ();
       force_next_insn = 0;
     }
-  reset_sched_cycles_p = pipelining_p;
   sel_region_finish (reset_sched_cycles_p);
 }
 

gcc/testsuite/ChangeLog

+2019-04-01  Andrey Belevantsev  <abel@ispras.ru>
+
+	PR rtl-optimization/85412
+	* gcc.dg/pr85412.c: New test.
+
 2019-04-01  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	PR c++/62207

gcc/testsuite/gcc.dg/pr85412.c

+/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O1 -fpeephole2 -fschedule-insns2 -fsel-sched-pipelining -fselective-scheduling2 -ftree-loop-if-convert -fno-if-conversion -fno-move-loop-invariants -fno-split-wide-types -fno-tree-dominator-opts" } */
+/* { dg-additional-options "-march=bonnell" { target x86_64-*-* } } */
+
+__int128 jv;
+
+void
+zm (__int128 g9, unsigned short int sm, short int hk)
+{
+  while (hk < 1)
+    {
+      if (jv == 0)
+        sm *= g9;
+
+      if (sm < jv)
+        hk = sm;
+
+      g9 |= sm == hk;
+    }
+}