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Commit 4ae234b0 by Geoffrey Keating Committed by Geoffrey Keating
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predicates.md (reg_or_arith_cint_operand): Delete. 

	* config/rs6000/predicates.md (reg_or_arith_cint_operand): Delete.
	(reg_or_add_cint_operand): Rename from reg_or_add_cint64_operand.
	Handle SImode.
	(reg_or_sub_cint_operand): Likewise.
	(mask_operand): Handle DImode.
	(mask64_operand): Delete.
	(and64_operand): Delete.
	* config/rs6000/rs6000.c (num_insns_constant): Use mask_operand
	instead of mask64_operand.
	(print_operand): Likewise.
	(rs6000_rtx_costs): Use mask_operand and reg_or_add_cint_operand and
	reg_or_sub_cint_operand instead of *64_* variants.
	* config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Use mask_operand
	instead of mask64_operand.
	* config/rs6000/rs6000.md: Use mask_operand and and_operand instead
	of *64_* variants.
	(FP): New.
	(add_op2): Delete.
	(add<mode>3): Use reg_or_add_cint_operand.
	(sub_op2): Delete.
	(sub<mode>3): Use reg_or_sub_cint_operand.
	(udiv<mode>3, div<mode>3, div<mode>3_no_mq, mod<mode>3,
	mov<mode>_internal2, mov<mode>, cmp<mode>, cmp<mode>,
	cmp<mode>_internal1, indirect_jump<mode>, ctr<mode>,
	ctr<mode>_internal1, ctr<mode>_internal2, ctr<mode>_internal5,
	ctr<mode>_internal6, save_fpregs_<mode>, return_internal_<mode>,
	return_and_restore_fpregs_<mode>, eh_set_lr_<mode>,
	various unnamed patterns): New.
	(udivsi3, divsi3, divsi3_no_mq, modsi3, movsi_internal2, movsi,
	cmpsi, cmpsi_internal1, indirect_jumpsi, ctrsi, ctrsi_internal1,
	ctrsi_internal2, ctrsi_internal5, ctrsi_internal6, save_fpregs_si,
	return_internal_si, return_and_restore_fpregs_si, eh_set_lr_si,
	udivdi3, divdi3, divdi3_no_mq, moddi3, movdi_internal2, movdi,
	cmpdi, cmpdi_internal1, indirect_jumpdi, ctrdi, ctrdi_internal1,
	ctrdi_internal2, ctrdi_internal5, ctrdi_internal6, save_fpregs_di,
	return_internal_di, return_and_restore_fpregs_di, eh_set_lr_di,
	movhi, movqi, cmpsf, cmpdf, cmptf, various unnamed patterns):
	Delete.

From-SVN: r100852
parent 58b82d2b
Showing with 84 additions and 75 deletions
gcc/ChangeLog
2005-06-11 Geoffrey Keating <geoffk@apple.com>
* config/rs6000/predicates.md (reg_or_arith_cint_operand): Delete.
(reg_or_add_cint_operand): Rename from reg_or_add_cint64_operand.
Handle SImode.
(reg_or_sub_cint_operand): Likewise.
(mask_operand): Handle DImode.
(mask64_operand): Delete.
(and64_operand): Delete.
* config/rs6000/rs6000.c (num_insns_constant): Use mask_operand
instead of mask64_operand.
(print_operand): Likewise.
(rs6000_rtx_costs): Use mask_operand and reg_or_add_cint_operand and
reg_or_sub_cint_operand instead of *64_* variants.
* config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Use mask_operand
instead of mask64_operand.
* config/rs6000/rs6000.md: Use mask_operand and and_operand instead
of *64_* variants.
(FP): New.
(add_op2): Delete.
(add<mode>3): Use reg_or_add_cint_operand.
(sub_op2): Delete.
(sub<mode>3): Use reg_or_sub_cint_operand.
(udiv<mode>3, div<mode>3, div<mode>3_no_mq, mod<mode>3,
mov<mode>_internal2, mov<mode>, cmp<mode>, cmp<mode>,
cmp<mode>_internal1, indirect_jump<mode>, ctr<mode>,
ctr<mode>_internal1, ctr<mode>_internal2, ctr<mode>_internal5,
ctr<mode>_internal6, save_fpregs_<mode>, return_internal_<mode>,
return_and_restore_fpregs_<mode>, eh_set_lr_<mode>,
various unnamed patterns): New.
(udivsi3, divsi3, divsi3_no_mq, modsi3, movsi_internal2, movsi,
cmpsi, cmpsi_internal1, indirect_jumpsi, ctrsi, ctrsi_internal1,
ctrsi_internal2, ctrsi_internal5, ctrsi_internal6, save_fpregs_si,
return_internal_si, return_and_restore_fpregs_si, eh_set_lr_si,
udivdi3, divdi3, divdi3_no_mq, moddi3, movdi_internal2, movdi,
cmpdi, cmpdi_internal1, indirect_jumpdi, ctrdi, ctrdi_internal1,
ctrdi_internal2, ctrdi_internal5, ctrdi_internal6, save_fpregs_di,
return_internal_di, return_and_restore_fpregs_di, eh_set_lr_di,
movhi, movqi, cmpsf, cmpdf, cmptf, various unnamed patterns):
Delete.
2005-06-11 Gabriel Dos Reis <gdr@integrable-solutions.net>
* rtl.h (to_rtx_code): Remove.
......
gcc/config/rs6000/predicates.md
......@@ -143,30 +143,25 @@
(TARGET_32BIT ? 'L' : 'J'))")
(match_operand 0 "gpc_reg_operand")))
;; Return 1 if op is a 32-bit signed constant integer valid for arithmetic
;; Return 1 if op is a constant integer valid for addition
;; or non-special register.
(define_predicate "reg_or_arith_cint_operand"
(define_predicate "reg_or_add_cint_operand"
(if_then_else (match_code "const_int")
(match_test "HOST_BITS_PER_WIDE_INT == 32
|| ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
< (unsigned HOST_WIDE_INT) 0x100000000ll)")
(match_operand 0 "gpc_reg_operand")))
;; Return 1 if op is a 32-bit signed constant integer valid for 64-bit addition
;; or non-special register.
(define_predicate "reg_or_add_cint64_operand"
(if_then_else (match_code "const_int")
(match_test "(HOST_BITS_PER_WIDE_INT == 32 && INTVAL (op) < 0x7fff8000)
(match_test "(HOST_BITS_PER_WIDE_INT == 32
&& (mode == SImode || INTVAL (op) < 0x7fff8000))
|| ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
< (unsigned HOST_WIDE_INT) 0x100000000ll)")
(match_operand 0 "gpc_reg_operand")))
;; Return 1 if op is a 32-bit constant integer valid for 64-bit subtraction
;; Return 1 if op is a constant integer valid for subtraction
;; or non-special register.
(define_predicate "reg_or_sub_cint64_operand"
(define_predicate "reg_or_sub_cint_operand"
(if_then_else (match_code "const_int")
(match_test "(HOST_BITS_PER_WIDE_INT == 32 && INTVAL (op) < 0x7fff8000)
|| ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
(match_test "(HOST_BITS_PER_WIDE_INT == 32
&& (mode == SImode || - INTVAL (op) < 0x7fff8000))
|| ((unsigned HOST_WIDE_INT) (- INTVAL (op)
+ (mode == SImode
? 0x80000000 : 0x80008000))
< (unsigned HOST_WIDE_INT) 0x100000000ll)")
(match_operand 0 "gpc_reg_operand")))
......@@ -439,10 +434,14 @@
(and (not (match_operand 0 "logical_operand"))
(match_operand 0 "reg_or_logical_cint_operand"))))
;; Return 1 if op is a constant that can be encoded in a 32-bit mask (no
;; more than two 1->0 or 0->1 transitions). Reject all ones and all
;; zeros, since these should have been optimized away and confuse the
;; making of MB and ME.
;; For SImode, return 1 if op is a constant that can be encoded in a
;; 32-bit mask (no more than two 1->0 or 0->1 transitions). Reject
;; all ones and all zeros, since these should have been optimized away
;; and confuse the making of MB and ME.
;; For DImode, return 1 if the operand is a constant that is a
;; PowerPC64 mask (no more than one 1->0 or 0->1 transitions). Reject
;; all zeros, since zero should have been optimized away and confuses
;; the making of MB and ME.
(define_predicate "mask_operand"
(match_code "const_int")
{
......@@ -452,7 +451,11 @@
/* Fail in 64-bit mode if the mask wraps around because the upper
32-bits of the mask will all be 1s, contrary to GCC's internal view. */
if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
if (mode == SImode && TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
return 0;
/* Reject all zeros or all ones in 32-bit mode. */
if (c == 0 || (mode == SImode && c == -1))
return 0;
/* We don't change the number of transitions by inverting,
......@@ -460,21 +463,20 @@
if (c & 1)
c = ~c;
/* Reject all zeros or all ones. */
if (c == 0)
return 0;
/* Find the first transition. */
lsb = c & -c;
/* Invert to look for a second transition. */
c = ~c;
if (mode == SImode)
{
/* Invert to look for a second transition. */
c = ~c;
/* Erase first transition. */
c &= -lsb;
/* Erase first transition. */
c &= -lsb;
/* Find the second transition (if any). */
lsb = c & -c;
/* Find the second transition (if any). */
lsb = c & -c;
}
/* Match if all the bits above are 1's (or c is zero). */
return c == -lsb;
......@@ -502,33 +504,7 @@
return c == -lsb;
})
;; Return 1 if the operand is a constant that is a PowerPC64 mask (no more
;; than one 1->0 or 0->1 transitions). Reject all zeros, since zero
;; should have been optimized away and confuses the making of MB and ME.
(define_predicate "mask64_operand"
(match_code "const_int")
{
HOST_WIDE_INT c, lsb;
c = INTVAL (op);
/* Reject all zeros. */
if (c == 0)
return 0;
/* We don't change the number of transitions by inverting,
so make sure we start with the LS bit zero. */
if (c & 1)
c = ~c;
/* Find the transition, and check that all bits above are 1's. */
lsb = c & -c;
/* Match if all the bits above are 1's (or c is zero). */
return c == -lsb;
})
;; Like mask64_operand, but allow up to three transitions. This
;; Like mask_operand, but allow up to three transitions. This
;; predicate is used by insn patterns that generate two rldicl or
;; rldicr machine insns.
(define_predicate "mask64_2_operand"
......@@ -537,15 +513,7 @@
return mask64_1or2_operand (op, mode, false);
})
;; Return 1 if the operand is either a non-special register or a constant
;; that can be used as the operand of a PowerPC64 logical AND insn.
(define_predicate "and64_operand"
(ior (match_operand 0 "mask64_operand")
(if_then_else (match_test "fixed_regs[CR0_REGNO]")
(match_operand 0 "gpc_reg_operand")
(match_operand 0 "logical_operand"))))
;; Like and64_operand, but also match constants that can be implemented
;; Like and_operand, but also match constants that can be implemented
;; with two rldicl or rldicr insns.
(define_predicate "and64_2_operand"
(ior (and (match_code "const_int")
......
gcc/config/rs6000/rs6000.c
......@@ -1948,7 +1948,7 @@ num_insns_constant (rtx op, enum machine_mode mode)
case CONST_INT:
#if HOST_BITS_PER_WIDE_INT == 64
if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
&& mask64_operand (op, mode))
&& mask_operand (op, mode))
return 2;
else
#endif
......@@ -1990,7 +1990,7 @@ num_insns_constant (rtx op, enum machine_mode mode)
|| (high == -1 && low < 0))
return num_insns_constant_wide (low);
else if (mask64_operand (op, mode))
else if (mask_operand (op, mode))
return 2;
else if (low == 0)
......@@ -9880,7 +9880,7 @@ print_operand (FILE *file, rtx x, int code)
/* PowerPC64 mask position. All 0's is excluded.
CONST_INT 32-bit mask is considered sign-extended so any
transition must occur within the CONST_INT, not on the boundary. */
if (! mask64_operand (x, DImode))
if (! mask_operand (x, DImode))
output_operand_lossage ("invalid %%S value");
uval = INT_LOWPART (x);
......@@ -17594,9 +17594,9 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
return true;
}
else if ((outer_code == PLUS
&& reg_or_add_cint64_operand (x, VOIDmode))
&& reg_or_add_cint_operand (x, VOIDmode))
|| (outer_code == MINUS
&& reg_or_sub_cint64_operand (x, VOIDmode))
&& reg_or_sub_cint_operand (x, VOIDmode))
|| ((outer_code == SET
|| outer_code == IOR
|| outer_code == XOR)
......@@ -17613,7 +17613,7 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
&& ((outer_code == AND
&& (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
|| CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
|| mask64_operand (x, DImode)))
|| mask_operand (x, DImode)))
|| ((outer_code == IOR || outer_code == XOR)
&& CONST_DOUBLE_HIGH (x) == 0
&& (CONST_DOUBLE_LOW (x)
......
gcc/config/rs6000/rs6000.h
......@@ -1099,14 +1099,14 @@ enum reg_class
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
: (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
: (C) == 'S' ? mask64_operand (OP, DImode) \
: (C) == 'S' ? mask_operand (OP, DImode) \
: (C) == 'T' ? mask_operand (OP, SImode) \
: (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
&& small_data_operand (OP, GET_MODE (OP))) \
: (C) == 't' ? (mask64_2_operand (OP, DImode) \
&& (fixed_regs[CR0_REGNO] \
|| !logical_operand (OP, DImode)) \
&& !mask64_operand (OP, DImode)) \
&& !mask_operand (OP, DImode)) \
: (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
: (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
: (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP))) \
......
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