Skip to content

R
riscv-gcc-1
Commit 4a5528cc by Uros Bizjak Committed by Uros Bizjak
Options

i386.md (maxmin_int): Rename code attribute from maxminiprefix and update all users. 

	* config/i386/i386.md (maxmin_int): Rename code attribute from
	maxminiprefix and update all users.
	(maxmin_float): Ditto from maxminfprefix.
	(logic): Ditto from logicprefix.
	(absneg_mnemonic): Ditto from absnegprefix.
	* config/i386/mmx.md: Update all users of maxminiprefix,
	maxminfprefix and loficprefix for rename.
	* config/i386/sse.md: Ditto.
	* config/i386/sync.md (sync_<code><mode>): Update for
	logicprefix rename.

From-SVN: r158350
parent 289fcbbd
Showing with 67 additions and 54 deletions
gcc/ChangeLog
2010-04-14 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (maxmin_int): Rename code attribute from
maxminiprefix and update all users.
(maxmin_float): Ditto from maxminfprefix.
(logic): Ditto from logicprefix.
(absneg_mnemonic): Ditto from absnegprefix.
* config/i386/mmx.md: Update all users of maxminiprefix,
maxminfprefix and loficprefix for rename.
* config/i386/sse.md: Ditto.
* config/i386/sync.md (sync_<code><mode>): Update for
logicprefix rename.
2010-04-14 Manuel López-Ibáñez <manu@gcc.gnu.org>
PR 42966
......
gcc/config/i386/i386.md
......@@ -713,16 +713,16 @@
(define_code_iterator maxmin [smax smin umax umin])
;; Base name for integer and FP insn mnemonic
(define_code_attr maxminiprefix [(smax "maxs") (smin "mins")
(umax "maxu") (umin "minu")])
(define_code_attr maxminfprefix [(smax "max") (smin "min")])
(define_code_attr maxmin_int [(smax "maxs") (smin "mins")
(umax "maxu") (umin "minu")])
(define_code_attr maxmin_float [(smax "max") (smin "min")])
;; Mapping of logic operators
(define_code_iterator any_logic [and ior xor])
(define_code_iterator any_or [ior xor])
;; Base name for insn mnemonic.
(define_code_attr logicprefix [(and "and") (ior "or") (xor "xor")])
(define_code_attr logic [(and "and") (ior "or") (xor "xor")])
;; Mapping of shift-right operators
(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
......@@ -746,7 +746,7 @@
(define_code_iterator absneg [abs neg])
;; Base name for x87 insn mnemonic.
(define_code_attr absnegprefix [(abs "abs") (neg "chs")])
(define_code_attr absneg_mnemonic [(abs "abs") (neg "chs")])
;; Used in signed and unsigned widening multiplications.
(define_code_iterator any_extend [sign_extend zero_extend])
......@@ -8785,7 +8785,7 @@
(match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
"<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
......@@ -8797,9 +8797,9 @@
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, QImode, operands)"
"@
<logicprefix>{b}\t{%2, %0|%0, %2}
<logicprefix>{b}\t{%2, %0|%0, %2}
<logicprefix>{l}\t{%k2, %k0|%k0, %k2}"
<logic>{b}\t{%2, %0|%0, %2}
<logic>{b}\t{%2, %0|%0, %2}
<logic>{l}\t{%k2, %k0|%k0, %k2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI,QI,SI")])
......@@ -8811,7 +8811,7 @@
(match_operand:SI 2 "general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
"<logicprefix>{l}\t{%2, %k0|%k0, %2}"
"<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
......@@ -8822,7 +8822,7 @@
(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
"<logicprefix>{l}\t{%2, %k0|%k0, %2}"
"<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
......@@ -8833,7 +8833,7 @@
(clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"<logicprefix>{b}\t{%1, %0|%0, %1}"
"<logic>{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
......@@ -8847,7 +8847,7 @@
(any_or:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
"<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
......@@ -8862,7 +8862,7 @@
(zero_extend:DI (any_or:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, SImode, operands)"
"<logicprefix>{l}\t{%2, %k0|%k0, %2}"
"<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
......@@ -8876,7 +8876,7 @@
(any_or:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, SImode, operands)"
"<logicprefix>{l}\t{%2, %k0|%k0, %2}"
"<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
......@@ -8890,7 +8890,7 @@
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCNOmode)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"<logicprefix>{b}\t{%1, %0|%0, %1}"
"<logic>{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
......@@ -8903,7 +8903,7 @@
(clobber (match_scratch:SWI 0 "=<r>"))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
"<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
......@@ -8919,7 +8919,7 @@
(match_operand 2 "const_int_operand" "n")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
"<logicprefix>{b}\t{%2, %h0|%h0, %2}"
"<logic>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "modrm" "1")
......@@ -8939,7 +8939,7 @@
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"<logicprefix>{b}\t{%2, %h0|%h0, %2}"
"<logic>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
......@@ -8958,7 +8958,7 @@
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"<logicprefix>{b}\t{%2, %h0|%h0, %2}"
"<logic>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
......@@ -8976,7 +8976,7 @@
(const_int 8))))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
"<logicprefix>{b}\t{%h2, %h0|%h0, %h2}"
"<logic>{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
......@@ -9366,7 +9366,7 @@
"TARGET_80387
&& (reload_completed
|| !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
"f<absnegprefix>"
"f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "<MODE>")])
......@@ -9375,7 +9375,7 @@
(absneg:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
"f<absnegprefix>"
"f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "DF")])
......@@ -9384,16 +9384,16 @@
(absneg:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387"
"f<absnegprefix>"
"f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
(define_insn "*<code>extenddfxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(absneg:XF (float_extend:XF
(match_operand:DF 1 "register_operand" "0"))))]
(match_operand:DF 1 "register_operand" "0"))))]
"TARGET_80387"
"f<absnegprefix>"
"f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
......@@ -16898,7 +16898,7 @@
(match_operand:MODEF 1 "nonimmediate_operand" "%x")
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"v<maxminfprefix>s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
"v<maxmin_float>s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
......@@ -16909,7 +16909,7 @@
(match_operand:MODEF 1 "nonimmediate_operand" "%0")
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"<maxminfprefix>s<ssemodefsuffix>\t{%2, %0|%0, %2}"
"<maxmin_float>s<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
......
gcc/config/i386/mmx.md
......@@ -396,7 +396,7 @@
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW && flag_finite_math_only
&& ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
"pf<maxminfprefix>\t{%2, %0|%0, %2}"
"pf<maxmin_float>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
......@@ -407,7 +407,7 @@
(match_operand:V2SF 1 "register_operand" "0")
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pf<maxminfprefix>\t{%2, %0|%0, %2}"
"pf<maxmin_float>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
......@@ -970,7 +970,7 @@
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"(TARGET_SSE || TARGET_3DNOW_A)
&& ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
"p<maxminiprefix>w\t{%2, %0|%0, %2}"
"p<maxmin_int>w\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
......@@ -989,7 +989,7 @@
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"(TARGET_SSE || TARGET_3DNOW_A)
&& ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
"p<maxminiprefix>b\t{%2, %0|%0, %2}"
"p<maxmin_int>b\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
......@@ -1099,7 +1099,7 @@
(match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
(match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"p<logicprefix>\t{%2, %0|%0, %2}"
"p<logic>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
......
gcc/config/i386/sse.md
......@@ -1015,7 +1015,7 @@
(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
"v<maxmin_float>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
......@@ -1027,7 +1027,7 @@
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
"<maxmin_float>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
......@@ -1037,7 +1037,7 @@
(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
"v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
"v<maxmin_float>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
......@@ -1048,7 +1048,7 @@
(match_operand:SSEMODEF2P 1 "register_operand" "0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
"<maxmin_float>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
......@@ -1061,7 +1061,7 @@
(match_dup 1)
(const_int 1)))]
"AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
"v<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
"v<maxmin_float>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sse")
(set_attr "prefix" "vex")
(set_attr "mode" "<ssescalarmode>")])
......@@ -1075,7 +1075,7 @@
(match_dup 1)
(const_int 1)))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
"<maxmin_float>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<ssescalarmode>")])
......@@ -1597,7 +1597,7 @@
(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"v<logicprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
"v<logic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
......@@ -1617,7 +1617,7 @@
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"<logicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
"<logic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<MODE>")])
......@@ -1673,7 +1673,7 @@
(match_operand:MODEF 1 "register_operand" "x")
(match_operand:MODEF 2 "register_operand" "x")))]
"AVX_FLOAT_MODE_P (<MODE>mode)"
"v<logicprefix>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
"v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<ssevecmode>")])
......@@ -1684,7 +1684,7 @@
(match_operand:MODEF 1 "register_operand" "0")
(match_operand:MODEF 2 "register_operand" "x")))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
"<logicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
"<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<ssevecmode>")])
......@@ -6031,7 +6031,7 @@
(match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
(match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"vp<maxminiprefix><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
"vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set (attr "prefix_extra")
(if_then_else
......@@ -6056,7 +6056,7 @@
(match_operand:V16QI 1 "nonimmediate_operand" "%0")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
"p<maxminiprefix>b\t{%2, %0|%0, %2}"
"p<maxmin_int>b\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
......@@ -6075,7 +6075,7 @@
(match_operand:V8HI 1 "nonimmediate_operand" "%0")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
"p<maxminiprefix>w\t{%2, %0|%0, %2}"
"p<maxmin_int>w\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
......@@ -6130,7 +6130,7 @@
(match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
"p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
......@@ -6186,7 +6186,7 @@
(match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
"p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
......@@ -6518,7 +6518,7 @@
(match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"v<logicprefix>ps\t{%2, %1, %0|%0, %1, %2}"
"v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecpsmode>")])
......@@ -6530,7 +6530,7 @@
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"<logicprefix>ps\t{%2, %0|%0, %2}"
"<logic>ps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "V4SF")])
......@@ -6541,7 +6541,7 @@
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"vp<logicprefix>\t{%2, %1, %0|%0, %1, %2}"
"vp<logic>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
......@@ -6552,7 +6552,7 @@
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"p<logicprefix>\t{%2, %0|%0, %2}"
"p<logic>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
......@@ -6571,7 +6571,7 @@
(match_operand:TF 1 "nonimmediate_operand" "%0")
(match_operand:TF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
"p<logicprefix>\t{%2, %0|%0, %2}"
"p<logic>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
......
gcc/config/i386/sync.md
......@@ -236,4 +236,4 @@
UNSPECV_LOCK))
(clobber (reg:CC FLAGS_REG))]
""
"lock{%;| }<logicprefix>{<imodesuffix>}\t{%1, %0|%0, %1}")
"lock{%;| }<logic>{<imodesuffix>}\t{%1, %0|%0, %1}")
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment