i386.md (*zero_extendsidi2): Enable alternative (?r, *Yj) also for 32bit target.

	* config/i386/i386.md (*zero_extendsidi2): Enable alternative (?r, *Yj)
	also for 32bit target.  Update insn attributes.
	(zero-extendsidi2 splitter): Allow all registers for operand 1.

From-SVN: r248757

gcc/ChangeLog

+2017-05-31  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*zero_extendsidi2): Enable alternative (?r, *Yj)
+	also for 32bit target.  Update insn attributes.
+	(zero-extendsidi2 splitter): Allow all registers for operand 1.
+
 2017-05-31  Sebastian Peryt  <sebastian.peryt@intel.com>
 
 	* config/i386/avx512fintrin.h (_mm_mask_max_sd)

gcc/config/i386/i386.md

@@ -3843,7 +3843,7 @@
   [(set (attr "isa")
      (cond [(eq_attr "alternative" "0,1,2")
 	      (const_string "nox64")
-	    (eq_attr "alternative" "3,7")
+	    (eq_attr "alternative" "3")
 	      (const_string "x64")
 	    (eq_attr "alternative" "9")
 	      (const_string "sse2")
@@ -3860,7 +3860,11 @@
 	      (const_string "multi")
 	    (eq_attr "alternative" "5,6")
 	      (const_string "mmxmov")
-	    (eq_attr "alternative" "7,8,9,10,11")
+	    (eq_attr "alternative" "7")
+	      (if_then_else (match_test "TARGET_64BIT")
+		(const_string "ssemov")
+		(const_string "multi"))
+	    (eq_attr "alternative" "8,9,10,11")
 	      (const_string "ssemov")
 	    (eq_attr "alternative" "12")
 	      (const_string "mskmov")
@@ -3881,7 +3885,10 @@
    (set (attr "mode")
      (cond [(eq_attr "alternative" "5,6")
 	      (const_string "DI")
-	    (eq_attr "alternative" "7,8,10,11")
+	    (and (eq_attr "alternative" "7")
+		 (match_test "TARGET_64BIT"))
+	      (const_string "TI")
+	    (eq_attr "alternative" "8,10,11")
 	      (const_string "TI")
 	   ]
 	   (const_string "SI")))])
@@ -3903,7 +3910,7 @@
 
 (define_split
   [(set (match_operand:DI 0 "nonimmediate_gr_operand")
-	(zero_extend:DI (match_operand:SI 1 "nonimmediate_gr_operand")))]
+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
   "!TARGET_64BIT && reload_completed
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   [(set (match_dup 3) (match_dup 1))