aarch64.md (mov<mode>:GPF): Don't call force_reg if op1 is an fp zero.

gcc/
	* config/aarch64/aarch64.md (mov<mode>:GPF): Don't call force_reg if
	op1 is an fp zero.
	(movsf_aarch64): Change condition from register_operand to
	aarch64_reg_or_fp_zero for op1.  Change type for alternative 6 to
	load1.  Change type for alternative 7 to store1.
	(movdf_aarch64): Likewise.
gcc/testsuite/
	* gcc.target/aarch64/fmovd-zero-mem.c: New.
	* gcc.target/aarch64/fmovd-zero-reg.c: New.
	* gcc.target/aarch64/fmovf-zero-mem.c: New.
	* gcc.target/aarch64/fmovf-zero-reg.c: New.
	* gcc.target/aarch64/fmovld-zero-mem.c: New.
	* gcc.target/aarch64/fmovld-zero-mem.c: New.
	* gcc.target/aarch64/fmovd-zero.c: Delete.
	* gcc.target/aarch64/fmovf-zero.c: Delete.

From-SVN: r224673

gcc/ChangeLog

+2015-06-19  Jim Wilson  <jim.wilson@linaro.org>
+
+	* config/aarch64/aarch64.md (mov<mode>:GPF): Don't call force_reg if
+	op1 is an fp zero.
+	(movsf_aarch64): Change condition from register_operand to
+	aarch64_reg_or_fp_zero for op1.  Change type for alternative 6 to
+	load1.  Change type for alternative 7 to store1.
+	(movdf_aarch64): Likewise.
+
 2015-06-19  James Greenhalgh  <james.greenhalgh@arm.com>
 
 	* config/vax/vax.md: Adjust sign/zero extend patterns to

gcc/config/aarch64/aarch64.md

@@ -986,7 +986,9 @@
 	FAIL;
      }
 
-    if (GET_CODE (operands[0]) == MEM)
+    if (GET_CODE (operands[0]) == MEM
+        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
+	      && aarch64_float_const_zero_rtx_p (operands[1])))
       operands[1] = force_reg (<MODE>mode, operands[1]);
   "
 )
@@ -995,7 +997,7 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w  ,w,m,r,m ,r")
 	(match_operand:SF 1 "general_operand"      "?rY, w,w,Ufc,m,w,m,rY,r"))]
   "TARGET_FLOAT && (register_operand (operands[0], SFmode)
-    || register_operand (operands[1], SFmode))"
+    || aarch64_reg_or_fp_zero (operands[1], SFmode))"
   "@
    fmov\\t%s0, %w1
    fmov\\t%w0, %s1
@@ -1007,14 +1009,14 @@
    str\\t%w1, %0
    mov\\t%w0, %w1"
   [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\
-                     f_loads,f_stores,f_loads,f_stores,mov_reg")]
+                     f_loads,f_stores,load1,store1,mov_reg")]
 )
 
 (define_insn "*movdf_aarch64"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w  ,w,m,r,m ,r")
 	(match_operand:DF 1 "general_operand"      "?rY, w,w,Ufc,m,w,m,rY,r"))]
   "TARGET_FLOAT && (register_operand (operands[0], DFmode)
-    || register_operand (operands[1], DFmode))"
+    || aarch64_reg_or_fp_zero (operands[1], DFmode))"
   "@
    fmov\\t%d0, %x1
    fmov\\t%x0, %d1
@@ -1026,7 +1028,7 @@
    str\\t%x1, %0
    mov\\t%x0, %x1"
   [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\
-                     f_loadd,f_stored,f_loadd,f_stored,mov_reg")]
+                     f_loadd,f_stored,load1,store1,mov_reg")]
 )
 
 (define_expand "movtf"

gcc/testsuite/ChangeLog

+2015-06-19  Jim Wilson  <jim.wilson@linaro.org>
+
+	* gcc.target/aarch64/fmovd-zero-mem.c: New.
+	* gcc.target/aarch64/fmovd-zero-reg.c: New.
+	* gcc.target/aarch64/fmovf-zero-mem.c: New.
+	* gcc.target/aarch64/fmovf-zero-reg.c: New.
+	* gcc.target/aarch64/fmovld-zero-mem.c: New.
+	* gcc.target/aarch64/fmovld-zero-mem.c: New.
+	* gcc.target/aarch64/fmovd-zero.c: Delete.
+	* gcc.target/aarch64/fmovf-zero.c: Delete.
+
 2015-06-19  James Greenhalgh  <james.greenhalgh@arm.com>
 
 	* gcc.target/vax/bswapdi-1.c: New.

gcc/testsuite/gcc.target/aarch64/fmovd-zero.c → gcc/testsuite/gcc.target/aarch64/fmovd-zero-mem.c

@@ -7,4 +7,4 @@ foo (double *output)
   *output = 0.0;
 }
 
-/* { dg-final { scan-assembler "fmov\\td\[0-9\]+, xzr" } } */
+/* { dg-final { scan-assembler "str\\txzr, \\\[x0\\\]" } } */

gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void bar (double);
+void
+foo (void)
+{
+  bar (0.0);
+}
+
+/* { dg-final { scan-assembler "fmov\\td0, xzr" } } */

gcc/testsuite/gcc.target/aarch64/fmovf-zero.c → gcc/testsuite/gcc.target/aarch64/fmovf-zero-mem.c

@@ -7,4 +7,4 @@ foo (float *output)
   *output = 0.0;
 }
 
-/* { dg-final { scan-assembler "fmov\\ts\[0-9\]+, wzr" } } */
+/* { dg-final { scan-assembler "str\\twzr, \\\[x0\\\]" } } */

gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void bar (float);
+void
+foo (void)
+{
+  bar (0.0);
+}
+
+/* { dg-final { scan-assembler "fmov\\ts0, wzr" } } */

gcc/testsuite/gcc.target/aarch64/fmovld-zero-mem.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (long double *output)
+{
+  *output = 0.0;
+}
+
+/* { dg-final { scan-assembler "stp\\txzr, xzr, \\\[x0\\\]" } } */

gcc/testsuite/gcc.target/aarch64/fmovld-zero-reg.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void bar (long double);
+void
+foo (void)
+{
+  bar (0.0);
+}
+
+/* { dg-final { scan-assembler "movi\\tv0\.2d, #0" } } */