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riscv-gcc-1
Commit 48c961ad by Kazu Hirata Committed by Kazu Hirata
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sh.h (PREDICATE_CODES): Add CONST to general_movsrc_operand. 

	* config/sh/sh.h (PREDICATE_CODES): Add CONST to
	general_movsrc_operand.

From-SVN: r97542
parent a9563ea3
Showing with 4 additions and 1 deletions
gcc/ChangeLog
...@@ -16,6 +16,9 @@ ...@@ -16,6 +16,9 @@
LABEL_REF to mcore_general_movsrc_operand. Add SYMBOL_REF to LABEL_REF to mcore_general_movsrc_operand. Add SYMBOL_REF to
mcore_call_address_operand. mcore_call_address_operand.
* config/sh/sh.h (PREDICATE_CODES): Add CONST to
general_movsrc_operand.
2005-04-04 Alan Modra <amodra@bigpond.net.au> 2005-04-04 Alan Modra <amodra@bigpond.net.au>
* passes.c (rest_of_handle_final): NULL unlikely_text_section_name * passes.c (rest_of_handle_final): NULL unlikely_text_section_name
......
gcc/config/sh/sh.h
...@@ -3355,7 +3355,7 @@ extern int rtx_equal_function_value_matters; ...@@ -3355,7 +3355,7 @@ extern int rtx_equal_function_value_matters;
{"fpscr_operand", {REG}}, \ {"fpscr_operand", {REG}}, \
{"fpul_operand", {REG}}, \ {"fpul_operand", {REG}}, \
{"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \ {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
{"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM, CONST }}, \
{"general_movdst_operand", {SUBREG, REG, MEM}}, \ {"general_movdst_operand", {SUBREG, REG, MEM}}, \
{"unaligned_load_operand", {MEM}}, \ {"unaligned_load_operand", {MEM}}, \
{"greater_comparison_operator", {GT,GE,GTU,GEU}}, \ {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
......
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