[AARCH64] use "arch_enabled" attribute for aarch64.

arm.md has some attributes "arch" and "arch_enabled" to aid enabling
and disabling insn alternatives based on the architecture being
targeted.  This patch introduces a similar attribute in the aarch64
backend.  The new attribute will be used to enable a new alternative
for the atomic_store insn in a future patch, but is an atomic change
in itself.

The new attribute has values "any", "fp", "fp16", "simd", and "sve".
These attribute values have been taken from the pre-existing
attributes "fp", "fp16", "simd", and "sve".

The standalone "fp" attribute has been reintroduced in terms of the
"arch" attribute as it's needed for the xgene1.md scheduling file --
the use in this file can't be changed to check for `(eq_attr "arch"
"fp")` as the file is reused by the arm.md machine description whose
'arch' attribute doesn't have an 'fp' value.

2018-08-23  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64.md (arches): New enum.
	(arch): New enum attr.
	(arch_enabled): New attr.
	(enabled): Now uses arch_enabled only.
	(simd, sve, fp16): Removed attribute.
	(fp): Attr now defined in terms of 'arch'.
	(*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64, *movti_aarch64,
	*movhf_aarch64, <optab><fcvt_target><GPF:mode>2,
	<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3,
	<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3): Merge 'fp' and 'simd'
	attributes into 'arch'.
	(*movsf_aarch64, *movdf_aarch64, *movtf_aarch64, *add<mode>3_aarch64,
	subdi3, neg<mode>2, <optab><mode>3, one_cmpl<mode>2,
	*<NLOGICAL:optab>_one_cmpl<mode>3, *xor_one_cmpl<mode>3,
	*aarch64_ashl_sisd_or_int_<mode>3, *aarch64_lshr_sisd_or_int_<mode>3,
	*aarch64_ashr_sisd_or_int_<mode>3, *aarch64_sisd_ushl): Convert use of
	'simd' attribute into 'arch'.
	(load_pair_sw_<SX:mode><SX2:mode>, load_pair_dw_<DX:mode><DX2:mode>,
	store_pair_sw_<SX:mode><SX2:mode>, store_pair_dw_<DX:mode><DX2:mode>):
	Convert use of 'fp' attribute to 'arch'.
	* config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>,
	move_lo_quad_internal_<mode>): (different modes) Merge 'fp' and 'simd'
	into 'arch'.
	(move_lo_quad_internal_be_<mode>, move_lo_quad_internal_be_<mode>):
	(different modes) Merge 'fp' and 'simd' into 'arch'.
	(*aarch64_combinez<mode>, *aarch64_combinez_be<mode>): Merge 'fp' and
	'simd' into 'arch'.

From-SVN: r263811

gcc/ChangeLog

+2018-08-23  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* config/aarch64/aarch64.md (arches): New enum.
+	(arch): New enum attr.
+	(arch_enabled): New attr.
+	(enabled): Now uses arch_enabled only.
+	(simd, sve, fp16): Removed attribute.
+	(fp): Attr now defined in terms of 'arch'.
+	(*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64, *movti_aarch64,
+	*movhf_aarch64, <optab><fcvt_target><GPF:mode>2,
+	<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3,
+	<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3): Merge 'fp' and 'simd'
+	attributes into 'arch'.
+	(*movsf_aarch64, *movdf_aarch64, *movtf_aarch64, *add<mode>3_aarch64,
+	subdi3, neg<mode>2, <optab><mode>3, one_cmpl<mode>2,
+	*<NLOGICAL:optab>_one_cmpl<mode>3, *xor_one_cmpl<mode>3,
+	*aarch64_ashl_sisd_or_int_<mode>3, *aarch64_lshr_sisd_or_int_<mode>3,
+	*aarch64_ashr_sisd_or_int_<mode>3, *aarch64_sisd_ushl): Convert use of
+	'simd' attribute into 'arch'.
+	(load_pair_sw_<SX:mode><SX2:mode>, load_pair_dw_<DX:mode><DX2:mode>,
+	store_pair_sw_<SX:mode><SX2:mode>, store_pair_dw_<DX:mode><DX2:mode>):
+	Convert use of 'fp' attribute to 'arch'.
+	* config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>,
+	move_lo_quad_internal_<mode>): (different modes) Merge 'fp' and 'simd'
+	into 'arch'.
+	(move_lo_quad_internal_be_<mode>, move_lo_quad_internal_be_<mode>):
+	(different modes) Merge 'fp' and 'simd' into 'arch'.
+	(*aarch64_combinez<mode>, *aarch64_combinez_be<mode>): Merge 'fp' and
+	'simd' into 'arch'.
+
 2018-08-23  Segher Boessenkool  <segher@kernel.crashing.org>
 
 	PR rtl-optimization/87026

gcc/config/aarch64/aarch64-simd.md

@@ -1352,9 +1352,8 @@
    fmov\\t%d0, %1
    dup\\t%d0, %1"
   [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
-   (set_attr "simd" "yes,*,yes")
-   (set_attr "fp" "*,yes,*")
-   (set_attr "length" "4")]
+   (set_attr "length" "4")
+   (set_attr "arch" "simd,fp,simd")]
 )
 
 (define_insn "move_lo_quad_internal_<mode>"
@@ -1368,9 +1367,8 @@
    fmov\\t%d0, %1
    dup\\t%d0, %1"
   [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
-   (set_attr "simd" "yes,*,yes")
-   (set_attr "fp" "*,yes,*")
-   (set_attr "length" "4")]
+   (set_attr "length" "4")
+   (set_attr "arch" "simd,fp,simd")]
 )
 
 (define_insn "move_lo_quad_internal_be_<mode>"
@@ -1384,9 +1382,8 @@
    fmov\\t%d0, %1
    dup\\t%d0, %1"
   [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
-   (set_attr "simd" "yes,*,yes")
-   (set_attr "fp" "*,yes,*")
-   (set_attr "length" "4")]
+   (set_attr "length" "4")
+   (set_attr "arch" "simd,fp,simd")]
 )
 
 (define_insn "move_lo_quad_internal_be_<mode>"
@@ -1400,9 +1397,8 @@
    fmov\\t%d0, %1
    dup\\t%d0, %1"
   [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
-   (set_attr "simd" "yes,*,yes")
-   (set_attr "fp" "*,yes,*")
-   (set_attr "length" "4")]
+   (set_attr "length" "4")
+   (set_attr "arch" "simd,fp,simd")]
 )
 
 (define_expand "move_lo_quad_<mode>"
@@ -3114,8 +3110,7 @@
    fmov\t%d0, %1
    ldr\\t%d0, %1"
   [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg")
-   (set_attr "simd" "yes,*,yes")
-   (set_attr "fp" "*,yes,*")]
+   (set_attr "arch" "simd,fp,simd")]
 )
 
 (define_insn "*aarch64_combinez_be<mode>"
@@ -3129,8 +3124,7 @@
    fmov\t%d0, %1
    ldr\\t%d0, %1"
   [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg")
-   (set_attr "simd" "yes,*,yes")
-   (set_attr "fp" "*,yes,*")]
+   (set_attr "arch" "simd,fp,simd")]
 )
 
 (define_expand "aarch64_combine<mode>"