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riscv-gcc-1
Commit 4883241c by Steve Ellcey Committed by Steve Ellcey
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ia64.h (HARD_REGNO_NREGS): Handle RFmode. 

	* config/ia64/ia64.h (HARD_REGNO_NREGS): Handle RFmode.
	(HARD_REGNO_MODE_OK): Ditto.
	(MODES_TIEABLE_P): Ditto.
	(HARD_REGNO_CALLER_SAVE_MODE): Ditto.
	(CLASS_MAX_NREGS): Ditto.
	* config/ia64/ia64.c (ia64_print_operand_address): Add R format.
	* config/ia64/ia64.md (divsf3_internal_thr): Removed.
	(divdf3_internal_thr): Removed.
	* config/ia64/div.md: New file.
	* config/ia64/constraints.md: Add H constraint.

From-SVN: r126930
parent be5b01f3
Showing with 38 additions and 124 deletions
gcc/ChangeLog
2007-07-25 Steve Ellcey <sje@cup.hp.com>
* config/ia64/ia64.h (HARD_REGNO_NREGS): Handle RFmode.
(HARD_REGNO_MODE_OK): Ditto.
(MODES_TIEABLE_P): Ditto.
(HARD_REGNO_CALLER_SAVE_MODE): Ditto.
(CLASS_MAX_NREGS): Ditto.
* config/ia64/ia64.c (ia64_print_operand_address): Add R format.
* config/ia64/ia64.md (divsf3_internal_thr): Removed.
(divdf3_internal_thr): Removed.
* config/ia64/div.md: New file.
* config/ia64/constraints.md: Add H constraint.
2007-07-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> 2007-07-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* sbitmap.c (sbitmap_verify_popcount, sbitmap_alloc_with_popcount, * sbitmap.c (sbitmap_verify_popcount, sbitmap_alloc_with_popcount,
......
gcc/config/ia64/constraints.md
...@@ -90,6 +90,11 @@ ...@@ -90,6 +90,11 @@
(and (match_code "const_double") (and (match_code "const_double")
(match_test "op == CONST0_RTX (mode) || op == CONST1_RTX (mode)"))) (match_test "op == CONST0_RTX (mode) || op == CONST1_RTX (mode)")))
(define_constraint "H"
"0.0"
(and (match_code "const_double")
(match_test "op == CONST0_RTX (mode)")))
;; Extra constraints ;; Extra constraints
;; Note that while this accepts mem, it only accepts non-volatile mem, ;; Note that while this accepts mem, it only accepts non-volatile mem,
......
gcc/config/ia64/ia64.c
...@@ -4496,6 +4496,7 @@ ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED, ...@@ -4496,6 +4496,7 @@ ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
O Append .acq for volatile load. O Append .acq for volatile load.
P Postincrement of a MEM. P Postincrement of a MEM.
Q Append .rel for volatile store. Q Append .rel for volatile store.
R Print .s .d or nothing for a single, double or no truncation.
S Shift amount for shladd instruction. S Shift amount for shladd instruction.
T Print an 8-bit sign extended number (K) as a 32-bit unsigned number T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
for Intel assembler. for Intel assembler.
...@@ -4636,6 +4637,17 @@ ia64_print_operand (FILE * file, rtx x, int code) ...@@ -4636,6 +4637,17 @@ ia64_print_operand (FILE * file, rtx x, int code)
fputs(".rel", file); fputs(".rel", file);
return; return;
case 'R':
if (x == CONST0_RTX (GET_MODE (x)))
fputs(".s", file);
else if (x == CONST1_RTX (GET_MODE (x)))
fputs(".d", file);
else if (x == CONST2_RTX (GET_MODE (x)))
;
else
output_operand_lossage ("invalid %%R value");
return;
case 'S': case 'S':
fprintf (file, "%d", exact_log2 (INTVAL (x))); fprintf (file, "%d", exact_log2 (INTVAL (x)));
return; return;
......
gcc/config/ia64/ia64.h
...@@ -645,6 +645,7 @@ while (0) ...@@ -645,6 +645,7 @@ while (0)
: PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \ : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \ : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
: FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \ : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
: FR_REGNO_P (REGNO) && (MODE) == RFmode ? 1 \
: FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \ : FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
...@@ -660,7 +661,7 @@ while (0) ...@@ -660,7 +661,7 @@ while (0)
: PR_REGNO_P (REGNO) ? \ : PR_REGNO_P (REGNO) ? \
(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \ (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
: GR_REGNO_P (REGNO) ? \ : GR_REGNO_P (REGNO) ? \
(MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode \ (MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \
: AR_REGNO_P (REGNO) ? (MODE) == DImode \ : AR_REGNO_P (REGNO) ? (MODE) == DImode \
: BR_REGNO_P (REGNO) ? (MODE) == DImode \ : BR_REGNO_P (REGNO) ? (MODE) == DImode \
: 0) : 0)
...@@ -677,15 +678,15 @@ while (0) ...@@ -677,15 +678,15 @@ while (0)
we can't tie it with any other modes. */ we can't tie it with any other modes. */
#define MODES_TIEABLE_P(MODE1, MODE2) \ #define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
&& ((((MODE1) == XFmode) || ((MODE1) == XCmode)) \ && ((((MODE1) == XFmode) || ((MODE1) == XCmode) || ((MODE1) == RFmode)) \
== (((MODE2) == XFmode) || ((MODE2) == XCmode))) \ == (((MODE2) == XFmode) || ((MODE2) == XCmode) || ((MODE1) == RFmode))) \
&& (((MODE1) == BImode) == ((MODE2) == BImode))) && (((MODE1) == BImode) == ((MODE2) == BImode)))
/* Specify the modes required to caller save a given hard regno. /* Specify the modes required to caller save a given hard regno.
We need to ensure floating pt regs are not saved as DImode. */ We need to ensure floating pt regs are not saved as DImode. */
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode \ ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode \
: choose_hard_reg_mode ((REGNO), (NREGS), false)) : choose_hard_reg_mode ((REGNO), (NREGS), false))
/* Handling Leaf Functions */ /* Handling Leaf Functions */
...@@ -883,6 +884,7 @@ enum reg_class ...@@ -883,6 +884,7 @@ enum reg_class
#define CLASS_MAX_NREGS(CLASS, MODE) \ #define CLASS_MAX_NREGS(CLASS, MODE) \
((MODE) == BImode && (CLASS) == PR_REGS ? 2 \ ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
: (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \ : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
: (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \
: (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \ : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
......
gcc/config/ia64/ia64.md
...@@ -3109,60 +3109,6 @@ ...@@ -3109,60 +3109,6 @@
} }
[(set_attr "predicable" "no")]) [(set_attr "predicable" "no")])
(define_insn_and_split "divsf3_internal_thr"
[(set (match_operand:SF 0 "fr_register_operand" "=&f")
(div:SF (match_operand:SF 1 "fr_register_operand" "f")
(match_operand:SF 2 "fr_register_operand" "f")))
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:XF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
(mult:XF (match_dup 8) (match_dup 6))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(plus:XF (mult:XF (match_dup 3) (match_dup 3))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
(plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 9)
(float_truncate:SF
(mult:XF (match_dup 7) (match_dup 6))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
(minus:XF (match_dup 7)
(mult:XF (match_dup 8) (match_dup 3))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(set (match_dup 0)
(float_truncate:SF
(plus:XF (mult:XF (match_dup 4) (match_dup 6))
(match_dup 3)))))
]
{
operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
operands[10] = CONST1_RTX (XFmode);
}
[(set_attr "predicable" "no")])
;; Inline square root. ;; Inline square root.
(define_insn "*sqrt_approx" (define_insn "*sqrt_approx"
...@@ -3615,72 +3561,6 @@ ...@@ -3615,72 +3561,6 @@
} }
[(set_attr "predicable" "no")]) [(set_attr "predicable" "no")])
(define_insn_and_split "divdf3_internal_thr"
[(set (match_operand:DF 0 "fr_register_operand" "=&f")
(div:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_register_operand" "f")))
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
(mult:XF (match_dup 8) (match_dup 6))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
(plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
(plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
(plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 9)
(float_truncate:DF
(mult:XF (match_dup 7) (match_dup 6))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
(minus:DF (match_dup 1)
(mult:DF (match_dup 2) (match_dup 9))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(set (match_dup 0)
(plus:DF (mult:DF (match_dup 4) (match_dup 0))
(match_dup 9))))
]
{
operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
operands[10] = CONST1_RTX (XFmode);
}
[(set_attr "predicable" "no")])
;; Inline square root. ;; Inline square root.
(define_expand "sqrtdf2" (define_expand "sqrtdf2"
...@@ -6541,3 +6421,5 @@ ...@@ -6541,3 +6421,5 @@
(include "vect.md") (include "vect.md")
;; Atomic operations ;; Atomic operations
(include "sync.md") (include "sync.md")
;; New division operations
(include "div.md")
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