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riscv-gcc-1
Commit 487e359c by Georg-Johann Lay Committed by Georg-Johann Lay
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avr.md: Tidy up empty "". 

	* config/avr/avr.md: Tidy up empty "".  Fix C code indentation.
	* config/avr/avr-fixed.md: Ditto.

From-SVN: r191436
parent d4c059d5
Showing with 147 additions and 186 deletions
gcc/ChangeLog
2012-09-18 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md: Tidy up empty "". Fix C code indentation.
* config/avr/avr-fixed.md: Ditto.
2012-09-18 Maciej W. Rozycki <macro@codesourcery.com> 2012-09-18 Maciej W. Rozycki <macro@codesourcery.com>
* config/rs6000/rs6000.c (print_operand) <'c'>: Remove. * config/rs6000/rs6000.c (print_operand) <'c'>: Remove.
......
gcc/config/avr/avr-fixed.md
...@@ -22,12 +22,12 @@ ...@@ -22,12 +22,12 @@
;; along with GCC; see the file COPYING3. If not see ;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. ;; <http://www.gnu.org/licenses/>.
(define_mode_iterator ALL1Q [(QQ "") (UQQ "")]) (define_mode_iterator ALL1Q [QQ UQQ])
(define_mode_iterator ALL2Q [(HQ "") (UHQ "")]) (define_mode_iterator ALL2Q [HQ UHQ])
(define_mode_iterator ALL2A [(HA "") (UHA "")]) (define_mode_iterator ALL2A [HA UHA])
(define_mode_iterator ALL2QA [(HQ "") (UHQ "") (define_mode_iterator ALL2QA [HQ UHQ
(HA "") (UHA "")]) HA UHA])
(define_mode_iterator ALL4A [(SA "") (USA "")]) (define_mode_iterator ALL4A [SA USA])
(define_mode_iterator ALL2S [HQ HA]) (define_mode_iterator ALL2S [HQ HA])
(define_mode_iterator ALL4S [SA SQ]) (define_mode_iterator ALL4S [SA SQ])
...@@ -38,22 +38,22 @@ ...@@ -38,22 +38,22 @@
;;; Conversions ;;; Conversions
(define_mode_iterator FIXED_A (define_mode_iterator FIXED_A
[(QQ "") (UQQ "") [QQ UQQ
(HQ "") (UHQ "") (HA "") (UHA "") HQ UHQ HA UHA
(SQ "") (USQ "") (SA "") (USA "") SQ USQ SA USA
(DQ "") (UDQ "") (DA "") (UDA "") DQ UDQ DA UDA
(TA "") (UTA "") TA UTA
(QI "") (HI "") (SI "") (DI "")]) QI HI SI DI])
;; Same so that be can build cross products ;; Same so that be can build cross products
(define_mode_iterator FIXED_B (define_mode_iterator FIXED_B
[(QQ "") (UQQ "") [QQ UQQ
(HQ "") (UHQ "") (HA "") (UHA "") HQ UHQ HA UHA
(SQ "") (USQ "") (SA "") (USA "") SQ USQ SA USA
(DQ "") (UDQ "") (DA "") (UDA "") DQ UDQ DA UDA
(TA "") (UTA "") TA UTA
(QI "") (HI "") (SI "") (DI "")]) QI HI SI DI])
(define_insn "fract<FIXED_B:mode><FIXED_A:mode>2" (define_insn "fract<FIXED_B:mode><FIXED_A:mode>2"
[(set (match_operand:FIXED_A 0 "register_operand" "=r") [(set (match_operand:FIXED_A 0 "register_operand" "=r")
......
gcc/config/avr/avr.md
...@@ -220,26 +220,26 @@ ...@@ -220,26 +220,26 @@
;; Define mode iterators ;; Define mode iterators
(define_mode_iterator QIHI [(QI "") (HI "")]) (define_mode_iterator QIHI [QI HI])
(define_mode_iterator QIHI2 [(QI "") (HI "")]) (define_mode_iterator QIHI2 [QI HI])
(define_mode_iterator QISI [(QI "") (HI "") (PSI "") (SI "")]) (define_mode_iterator QISI [QI HI PSI SI])
(define_mode_iterator QIDI [(QI "") (HI "") (PSI "") (SI "") (DI "")]) (define_mode_iterator QIDI [QI HI PSI SI DI])
(define_mode_iterator HISI [(HI "") (PSI "") (SI "")]) (define_mode_iterator HISI [HI PSI SI])
(define_mode_iterator ALL1 [(QI "") (QQ "") (UQQ "")]) (define_mode_iterator ALL1 [QI QQ UQQ])
(define_mode_iterator ALL2 [(HI "") (HQ "") (UHQ "") (HA "") (UHA "")]) (define_mode_iterator ALL2 [HI HQ UHQ HA UHA])
(define_mode_iterator ALL4 [(SI "") (SQ "") (USQ "") (SA "") (USA "")]) (define_mode_iterator ALL4 [SI SQ USQ SA USA])
;; All supported move-modes ;; All supported move-modes
(define_mode_iterator MOVMODE [(QI "") (HI "") (SI "") (SF "") (PSI "") (define_mode_iterator MOVMODE [QI QQ UQQ
(QQ "") (UQQ "") HI HQ UHQ HA UHA
(HQ "") (UHQ "") (HA "") (UHA "") SI SQ USQ SA USA
(SQ "") (USQ "") (SA "") (USA "")]) SF PSI])
;; Supported ordered modes that are 2, 3, 4 bytes wide ;; Supported ordered modes that are 2, 3, 4 bytes wide
(define_mode_iterator ORDERED234 [(HI "") (SI "") (PSI "") (define_mode_iterator ORDERED234 [HI SI PSI
(HQ "") (UHQ "") (HA "") (UHA "") HQ UHQ HA UHA
(SQ "") (USQ "") (SA "") (USA "")]) SQ USQ SA USA])
;; Define code iterators ;; Define code iterators
;; Define two incarnations so that we can build the cross product. ;; Define two incarnations so that we can build the cross product.
...@@ -305,8 +305,8 @@ ...@@ -305,8 +305,8 @@
gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
gen_int_mode (STARTING_FRAME_OFFSET, gen_int_mode (STARTING_FRAME_OFFSET,
Pmode))); Pmode)));
/* This might change the hard frame pointer in ways that aren't /* ; This might change the hard frame pointer in ways that aren't
apparent to early optimization passes, so force a clobber. */ ; apparent to early optimization passes, so force a clobber. */
emit_clobber (hard_frame_pointer_rtx); emit_clobber (hard_frame_pointer_rtx);
DONE; DONE;
}) })
...@@ -321,25 +321,25 @@ ...@@ -321,25 +321,25 @@
(use (match_operand 2 "general_operand")) (use (match_operand 2 "general_operand"))
(use (match_operand 3 "general_operand"))] (use (match_operand 3 "general_operand"))]
"" ""
{ {
rtx r_label = copy_to_reg (operands[1]); rtx r_label = copy_to_reg (operands[1]);
rtx r_fp = operands[3]; rtx r_fp = operands[3];
rtx r_sp = operands[2]; rtx r_sp = operands[2];
emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode))); emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
emit_move_insn (hard_frame_pointer_rtx, r_fp); emit_move_insn (hard_frame_pointer_rtx, r_fp);
emit_stack_restore (SAVE_NONLOCAL, r_sp); emit_stack_restore (SAVE_NONLOCAL, r_sp);
emit_use (hard_frame_pointer_rtx); emit_use (hard_frame_pointer_rtx);
emit_use (stack_pointer_rtx); emit_use (stack_pointer_rtx);
emit_indirect_jump (r_label); emit_indirect_jump (r_label);
DONE; DONE;
}) })
;; "pushqi1" ;; "pushqi1"
;; "pushqq1" "pushuqq1" ;; "pushqq1" "pushuqq1"
...@@ -353,44 +353,42 @@ ...@@ -353,44 +353,42 @@
[(set_attr "length" "1,1")]) [(set_attr "length" "1,1")])
;; All modes for a multi-byte push. We must include complex modes here too, ;; All modes for a multi-byte push. We must include complex modes here too,
;; lest emit_single_push_insn "helpfully " create the auto-inc itself. ;; lest emit_single_push_insn "helpfully" create the auto-inc itself.
(define_mode_iterator MPUSH (define_mode_iterator MPUSH
[(CQI "") [CQI
(HI "") (CHI "") HI CHI HA UHA HQ UHQ
(PSI "") SI CSI SA USA SQ USQ
(SI "") (CSI "") DI CDI DA UDA DQ UDQ
(DI "") (CDI "") TA UTA
(SF "") (SC "") SF SC
(HA "") (UHA "") (HQ "") (UHQ "") PSI])
(SA "") (USA "") (SQ "") (USQ "")
(DA "") (UDA "") (DQ "") (UDQ "")
(TA "") (UTA "")])
(define_expand "push<mode>1" (define_expand "push<mode>1"
[(match_operand:MPUSH 0 "" "")] [(match_operand:MPUSH 0 "" "")]
"" ""
{ {
int i; int i;
for (i = GET_MODE_SIZE (<MODE>mode) - 1; i >= 0; --i) for (i = GET_MODE_SIZE (<MODE>mode) - 1; i >= 0; --i)
{ {
rtx part = simplify_gen_subreg (QImode, operands[0], <MODE>mode, i); rtx part = simplify_gen_subreg (QImode, operands[0], <MODE>mode, i);
if (part != const0_rtx) if (part != const0_rtx)
part = force_reg (QImode, part); part = force_reg (QImode, part);
emit_insn (gen_pushqi1 (part)); emit_insn (gen_pushqi1 (part));
} }
DONE; DONE;
}) })
;; Notice a special-case when adding N to SP where N results in a ;; Notice a special-case when adding N to SP where N results in a
;; zero REG_ARGS_SIZE. This is equivalent to a move from FP. ;; zero REG_ARGS_SIZE. This is equivalent to a move from FP.
(define_split (define_split
[(set (reg:HI REG_SP) (match_operand:HI 0 "register_operand" ""))] [(set (reg:HI REG_SP)
(match_operand:HI 0 "register_operand" ""))]
"reload_completed "reload_completed
&& frame_pointer_needed && frame_pointer_needed
&& !cfun->calls_alloca && !cfun->calls_alloca
&& find_reg_note (insn, REG_ARGS_SIZE, const0_rtx)" && find_reg_note (insn, REG_ARGS_SIZE, const0_rtx)"
[(set (reg:HI REG_SP) (reg:HI REG_Y))] [(set (reg:HI REG_SP)
"") (reg:HI REG_Y))])
;;======================================================================== ;;========================================================================
;; Move stuff around ;; Move stuff around
...@@ -775,9 +773,9 @@ ...@@ -775,9 +773,9 @@
(match_operand:ALL1 1 "even_register_operand" "")) (match_operand:ALL1 1 "even_register_operand" ""))
(set (match_operand:ALL1 2 "odd_register_operand" "") (set (match_operand:ALL1 2 "odd_register_operand" "")
(match_operand:ALL1 3 "odd_register_operand" ""))] (match_operand:ALL1 3 "odd_register_operand" ""))]
"(AVR_HAVE_MOVW "AVR_HAVE_MOVW
&& REGNO (operands[0]) == REGNO (operands[2]) - 1 && REGNO (operands[0]) == REGNO (operands[2]) - 1
&& REGNO (operands[1]) == REGNO (operands[3]) - 1)" && REGNO (operands[1]) == REGNO (operands[3]) - 1"
[(set (match_dup 4) [(set (match_dup 4)
(match_dup 5))] (match_dup 5))]
{ {
...@@ -790,9 +788,9 @@ ...@@ -790,9 +788,9 @@
(match_operand:ALL1 1 "odd_register_operand" "")) (match_operand:ALL1 1 "odd_register_operand" ""))
(set (match_operand:ALL1 2 "even_register_operand" "") (set (match_operand:ALL1 2 "even_register_operand" "")
(match_operand:ALL1 3 "even_register_operand" ""))] (match_operand:ALL1 3 "even_register_operand" ""))]
"(AVR_HAVE_MOVW "AVR_HAVE_MOVW
&& REGNO (operands[2]) == REGNO (operands[0]) - 1 && REGNO (operands[2]) == REGNO (operands[0]) - 1
&& REGNO (operands[3]) == REGNO (operands[1]) - 1)" && REGNO (operands[3]) == REGNO (operands[1]) - 1"
[(set (match_dup 4) [(set (match_dup 4)
(match_dup 5))] (match_dup 5))]
{ {
...@@ -812,8 +810,7 @@ ...@@ -812,8 +810,7 @@
&& operands[1] != constm1_rtx" && operands[1] != constm1_rtx"
[(parallel [(set (match_dup 0) [(parallel [(set (match_dup 0)
(match_dup 1)) (match_dup 1))
(clobber (match_dup 2))])] (clobber (match_dup 2))])])
"")
;; '*' because it is not used in rtl generation. ;; '*' because it is not used in rtl generation.
(define_insn "*reload_inpsi" (define_insn "*reload_inpsi"
...@@ -1481,9 +1478,7 @@ ...@@ -1481,9 +1478,7 @@
(set (reg:QI 22) (match_operand:QI 2 "register_operand" "")) (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
(parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
(clobber (reg:QI 22))]) (clobber (reg:QI 22))])
(set (match_operand:QI 0 "register_operand" "") (reg:QI 24))] (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))])
""
"")
(define_insn "*mulqi3_call" (define_insn "*mulqi3_call"
[(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
...@@ -1684,8 +1679,7 @@ ...@@ -1684,8 +1679,7 @@
(set (match_dup 0) (set (match_dup 0)
(plus:QI (mult:QI (match_dup 1) (plus:QI (mult:QI (match_dup 1)
(match_dup 4)) (match_dup 4))
(match_dup 3)))] (match_dup 3)))])
"")
(define_insn_and_split "*msubqi4.const" (define_insn_and_split "*msubqi4.const"
[(set (match_operand:QI 0 "register_operand" "=r") [(set (match_operand:QI 0 "register_operand" "=r")
...@@ -1702,8 +1696,7 @@ ...@@ -1702,8 +1696,7 @@
(set (match_dup 0) (set (match_dup 0)
(minus:QI (match_dup 3) (minus:QI (match_dup 3)
(mult:QI (match_dup 1) (mult:QI (match_dup 1)
(match_dup 4))))] (match_dup 4))))])
"")
;****************************************************************************** ;******************************************************************************
...@@ -2213,9 +2206,7 @@ ...@@ -2213,9 +2206,7 @@
(parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22))) (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
(clobber (reg:HI 22)) (clobber (reg:HI 22))
(clobber (reg:QI 21))]) (clobber (reg:QI 21))])
(set (match_operand:HI 0 "register_operand" "") (reg:HI 24))] (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))])
""
"")
(define_insn "*mulhi3_call" (define_insn "*mulhi3_call"
[(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22))) [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
...@@ -2389,8 +2380,7 @@ ...@@ -2389,8 +2380,7 @@
(mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26)))) (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
(reg:SI 18))) (reg:SI 18)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 22))] (reg:SI 22))])
"")
;; "mulhisi3" ;; "mulhisi3"
;; "umulhisi3" ;; "umulhisi3"
...@@ -2400,8 +2390,7 @@ ...@@ -2400,8 +2390,7 @@
(any_extend:SI (match_operand:HI 2 "register_operand" "")))) (any_extend:SI (match_operand:HI 2 "register_operand" ""))))
(clobber (reg:HI 26)) (clobber (reg:HI 26))
(clobber (reg:DI 18))])] (clobber (reg:DI 18))])]
"AVR_HAVE_MUL" "AVR_HAVE_MUL")
"")
(define_expand "usmulhisi3" (define_expand "usmulhisi3"
[(parallel [(set (match_operand:SI 0 "register_operand" "") [(parallel [(set (match_operand:SI 0 "register_operand" "")
...@@ -2409,8 +2398,7 @@ ...@@ -2409,8 +2398,7 @@
(sign_extend:SI (match_operand:HI 2 "register_operand" "")))) (sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
(clobber (reg:HI 26)) (clobber (reg:HI 26))
(clobber (reg:DI 18))])] (clobber (reg:DI 18))])]
"AVR_HAVE_MUL" "AVR_HAVE_MUL")
"")
;; "*uumulqihisi3" "*uumulhiqisi3" "*uumulhihisi3" "*uumulqiqisi3" ;; "*uumulqihisi3" "*uumulhiqisi3" "*uumulhihisi3" "*uumulqiqisi3"
;; "*usmulqihisi3" "*usmulhiqisi3" "*usmulhihisi3" "*usmulqiqisi3" ;; "*usmulqihisi3" "*usmulhiqisi3" "*usmulhihisi3" "*usmulqiqisi3"
...@@ -2482,8 +2470,7 @@ ...@@ -2482,8 +2470,7 @@
(clobber (reg:HI 22))]) (clobber (reg:HI 22))])
(set (match_operand:HI 0 "register_operand" "") (set (match_operand:HI 0 "register_operand" "")
(reg:HI 24))] (reg:HI 24))]
"AVR_HAVE_MUL" "AVR_HAVE_MUL")
"")
(define_insn "*mulsi3_call" (define_insn "*mulsi3_call"
...@@ -2577,8 +2564,7 @@ ...@@ -2577,8 +2564,7 @@
(clobber (reg:QI 22)) (clobber (reg:QI 22))
(clobber (reg:QI 23))]) (clobber (reg:QI 23))])
(set (match_dup 0) (reg:QI 24)) (set (match_dup 0) (reg:QI 24))
(set (match_dup 3) (reg:QI 25))] (set (match_dup 3) (reg:QI 25))])
"")
(define_insn "*divmodqi4_call" (define_insn "*divmodqi4_call"
[(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22))) [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
...@@ -2609,8 +2595,7 @@ ...@@ -2609,8 +2595,7 @@
(set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22))) (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
(clobber (reg:QI 23))]) (clobber (reg:QI 23))])
(set (match_dup 0) (reg:QI 24)) (set (match_dup 0) (reg:QI 24))
(set (match_dup 3) (reg:QI 25))] (set (match_dup 3) (reg:QI 25))])
"")
(define_insn "*udivmodqi4_call" (define_insn "*udivmodqi4_call"
[(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22))) [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
...@@ -2641,8 +2626,7 @@ ...@@ -2641,8 +2626,7 @@
(clobber (reg:HI 26)) (clobber (reg:HI 26))
(clobber (reg:QI 21))]) (clobber (reg:QI 21))])
(set (match_dup 0) (reg:HI 22)) (set (match_dup 0) (reg:HI 22))
(set (match_dup 3) (reg:HI 24))] (set (match_dup 3) (reg:HI 24))])
"")
(define_insn "*divmodhi4_call" (define_insn "*divmodhi4_call"
[(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22))) [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
...@@ -2674,8 +2658,7 @@ ...@@ -2674,8 +2658,7 @@
(clobber (reg:HI 26)) (clobber (reg:HI 26))
(clobber (reg:QI 21))]) (clobber (reg:QI 21))])
(set (match_dup 0) (reg:HI 22)) (set (match_dup 0) (reg:HI 22))
(set (match_dup 3) (reg:HI 24))] (set (match_dup 3) (reg:HI 24))])
"")
(define_insn "*udivmodhi4_call" (define_insn "*udivmodhi4_call"
[(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22))) [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
...@@ -2907,8 +2890,7 @@ ...@@ -2907,8 +2890,7 @@
(clobber (reg:HI 26)) (clobber (reg:HI 26))
(clobber (reg:HI 30))]) (clobber (reg:HI 30))])
(set (match_dup 0) (reg:SI 18)) (set (match_dup 0) (reg:SI 18))
(set (match_dup 3) (reg:SI 22))] (set (match_dup 3) (reg:SI 22))])
"")
(define_insn "*divmodsi4_call" (define_insn "*divmodsi4_call"
[(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18))) [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
...@@ -2940,8 +2922,7 @@ ...@@ -2940,8 +2922,7 @@
(clobber (reg:HI 26)) (clobber (reg:HI 26))
(clobber (reg:HI 30))]) (clobber (reg:HI 30))])
(set (match_dup 0) (reg:SI 18)) (set (match_dup 0) (reg:SI 18))
(set (match_dup 3) (reg:SI 22))] (set (match_dup 3) (reg:SI 22))])
"")
(define_insn "*udivmodsi4_call" (define_insn "*udivmodsi4_call"
[(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18))) [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
...@@ -3609,8 +3590,7 @@ ...@@ -3609,8 +3590,7 @@
[(parallel [(set (match_dup 0) [(parallel [(set (match_dup 0)
(ashift:ALL4 (match_dup 1) (ashift:ALL4 (match_dup 1)
(match_dup 2))) (match_dup 2)))
(clobber (match_dup 3))])] (clobber (match_dup 3))])])
"")
;; "*ashlsi3_const" ;; "*ashlsi3_const"
;; "*ashlsq3_const" "*ashlusq3_const" ;; "*ashlsq3_const" "*ashlusq3_const"
...@@ -4351,7 +4331,7 @@ ...@@ -4351,7 +4331,7 @@
[(set (cc0) [(set (cc0)
(compare (neg:QI (match_operand:QI 0 "register_operand" "r")) (compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
(const_int 0)))] (const_int 0)))]
"(!flag_wrapv && !flag_trapv && flag_strict_overflow)" "!flag_wrapv && !flag_trapv && flag_strict_overflow"
"cp __zero_reg__,%0" "cp __zero_reg__,%0"
[(set_attr "cc" "compare") [(set_attr "cc" "compare")
(set_attr "length" "1")]) (set_attr "length" "1")])
...@@ -4369,7 +4349,7 @@ ...@@ -4369,7 +4349,7 @@
[(set (cc0) [(set (cc0)
(compare (neg:HI (match_operand:HI 0 "register_operand" "r")) (compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
(const_int 0)))] (const_int 0)))]
"(!flag_wrapv && !flag_trapv && flag_strict_overflow)" "!flag_wrapv && !flag_trapv && flag_strict_overflow"
"cp __zero_reg__,%A0 "cp __zero_reg__,%A0
cpc __zero_reg__,%B0" cpc __zero_reg__,%B0"
[(set_attr "cc" "compare") [(set_attr "cc" "compare")
...@@ -4411,7 +4391,7 @@ ...@@ -4411,7 +4391,7 @@
[(set (cc0) [(set (cc0)
(compare (neg:SI (match_operand:SI 0 "register_operand" "r")) (compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
(const_int 0)))] (const_int 0)))]
"(!flag_wrapv && !flag_trapv && flag_strict_overflow)" "!flag_wrapv && !flag_trapv && flag_strict_overflow"
"cp __zero_reg__,%A0 "cp __zero_reg__,%A0
cpc __zero_reg__,%B0 cpc __zero_reg__,%B0
cpc __zero_reg__,%C0 cpc __zero_reg__,%C0
...@@ -4654,8 +4634,7 @@ ...@@ -4654,8 +4634,7 @@
(const_int 7)) (const_int 7))
(const_int 0)) (const_int 0))
(label_ref (match_dup 1)) (label_ref (match_dup 1))
(pc)))] (pc)))])
"")
(define_peephole2 (define_peephole2
[(set (cc0) (compare (match_operand:QI 0 "register_operand" "") [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
...@@ -4669,8 +4648,7 @@ ...@@ -4669,8 +4648,7 @@
(const_int 7)) (const_int 7))
(const_int 0)) (const_int 0))
(label_ref (match_dup 1)) (label_ref (match_dup 1))
(pc)))] (pc)))])
"")
(define_peephole2 (define_peephole2
[(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "") [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
...@@ -4683,8 +4661,7 @@ ...@@ -4683,8 +4661,7 @@
[(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768)) [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
(const_int 0)) (const_int 0))
(label_ref (match_dup 1)) (label_ref (match_dup 1))
(pc)))] (pc)))])
"")
(define_peephole2 (define_peephole2
[(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "") [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
...@@ -4697,8 +4674,7 @@ ...@@ -4697,8 +4674,7 @@
[(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768)) [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
(const_int 0)) (const_int 0))
(label_ref (match_dup 1)) (label_ref (match_dup 1))
(pc)))] (pc)))])
"")
(define_peephole2 (define_peephole2
[(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
...@@ -4712,7 +4688,7 @@ ...@@ -4712,7 +4688,7 @@
(const_int 0)) (const_int 0))
(label_ref (match_dup 1)) (label_ref (match_dup 1))
(pc)))] (pc)))]
"operands[2] = GEN_INT (-2147483647 - 1);") "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
(define_peephole2 (define_peephole2
[(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
...@@ -4726,7 +4702,7 @@ ...@@ -4726,7 +4702,7 @@
(const_int 0)) (const_int 0))
(label_ref (match_dup 1)) (label_ref (match_dup 1))
(pc)))] (pc)))]
"operands[2] = GEN_INT (-2147483647 - 1);") "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
;; ************************************************************************ ;; ************************************************************************
;; Implementation of conditional jumps here. ;; Implementation of conditional jumps here.
...@@ -4840,45 +4816,37 @@ ...@@ -4840,45 +4816,37 @@
;; call ;; call
;; Operand 1 not used on the AVR.
;; Operand 2 is 1 for tail-call, 0 otherwise.
(define_expand "call" (define_expand "call"
[(parallel[(call (match_operand:HI 0 "call_insn_operand" "") [(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
(match_operand:HI 1 "general_operand" "")) (match_operand:HI 1 "general_operand" ""))
(use (const_int 0))])] (use (const_int 0))])])
;; Operand 1 not used on the AVR.
;; Operand 2 is 1 for tail-call, 0 otherwise.
""
"")
;; Operand 1 not used on the AVR.
;; Operand 2 is 1 for tail-call, 0 otherwise.
(define_expand "sibcall" (define_expand "sibcall"
[(parallel[(call (match_operand:HI 0 "call_insn_operand" "") [(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
(match_operand:HI 1 "general_operand" "")) (match_operand:HI 1 "general_operand" ""))
(use (const_int 1))])] (use (const_int 1))])])
;; Operand 1 not used on the AVR.
;; Operand 2 is 1 for tail-call, 0 otherwise.
""
"")
;; call value ;; call value
;; Operand 2 not used on the AVR.
;; Operand 3 is 1 for tail-call, 0 otherwise.
(define_expand "call_value" (define_expand "call_value"
[(parallel[(set (match_operand 0 "register_operand" "") [(parallel[(set (match_operand 0 "register_operand" "")
(call (match_operand:HI 1 "call_insn_operand" "") (call (match_operand:HI 1 "call_insn_operand" "")
(match_operand:HI 2 "general_operand" ""))) (match_operand:HI 2 "general_operand" "")))
(use (const_int 0))])] (use (const_int 0))])])
;; Operand 2 not used on the AVR.
;; Operand 3 is 1 for tail-call, 0 otherwise.
""
"")
;; Operand 2 not used on the AVR.
;; Operand 3 is 1 for tail-call, 0 otherwise.
(define_expand "sibcall_value" (define_expand "sibcall_value"
[(parallel[(set (match_operand 0 "register_operand" "") [(parallel[(set (match_operand 0 "register_operand" "")
(call (match_operand:HI 1 "call_insn_operand" "") (call (match_operand:HI 1 "call_insn_operand" "")
(match_operand:HI 2 "general_operand" ""))) (match_operand:HI 2 "general_operand" "")))
(use (const_int 1))])] (use (const_int 1))])])
;; Operand 2 not used on the AVR.
;; Operand 3 is 1 for tail-call, 0 otherwise.
""
"")
(define_insn "call_insn" (define_insn "call_insn"
[(parallel[(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "z,s,z,s")) [(parallel[(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "z,s,z,s"))
...@@ -5069,11 +5037,11 @@ ...@@ -5069,11 +5037,11 @@
(label_ref (match_operand 2 "" "")) (label_ref (match_operand 2 "" ""))
(pc)))] (pc)))]
"" ""
{ {
operands[3] = operands[2]; operands[3] = operands[2];
operands[2] = GEN_INT (7); operands[2] = GEN_INT (7);
return avr_out_sbxx_branch (insn, operands); return avr_out_sbxx_branch (insn, operands);
} }
[(set (attr "length") [(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046)) (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
(le (minus (pc) (match_dup 2)) (const_int 2046))) (le (minus (pc) (match_dup 2)) (const_int 2046)))
...@@ -5117,11 +5085,11 @@ ...@@ -5117,11 +5085,11 @@
(label_ref (match_operand 2 "" "")) (label_ref (match_operand 2 "" ""))
(pc)))] (pc)))]
"" ""
{ {
operands[3] = operands[2]; operands[3] = operands[2];
operands[2] = GEN_INT (7); operands[2] = GEN_INT (7);
return avr_out_sbxx_branch (insn, operands); return avr_out_sbxx_branch (insn, operands);
} }
[(set (attr "length") [(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046)) (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
(le (minus (pc) (match_dup 2)) (const_int 2045))) (le (minus (pc) (match_dup 2)) (const_int 2045)))
...@@ -5479,29 +5447,29 @@ ...@@ -5479,29 +5447,29 @@
(define_insn "return_from_epilogue" (define_insn "return_from_epilogue"
[(return)] [(return)]
"(reload_completed "reload_completed
&& cfun->machine && cfun->machine
&& !(cfun->machine->is_interrupt || cfun->machine->is_signal) && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
&& !cfun->machine->is_naked)" && !cfun->machine->is_naked"
"ret" "ret"
[(set_attr "cc" "none") [(set_attr "cc" "none")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "return_from_interrupt_epilogue" (define_insn "return_from_interrupt_epilogue"
[(return)] [(return)]
"(reload_completed "reload_completed
&& cfun->machine && cfun->machine
&& (cfun->machine->is_interrupt || cfun->machine->is_signal) && (cfun->machine->is_interrupt || cfun->machine->is_signal)
&& !cfun->machine->is_naked)" && !cfun->machine->is_naked"
"reti" "reti"
[(set_attr "cc" "none") [(set_attr "cc" "none")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "return_from_naked_epilogue" (define_insn "return_from_naked_epilogue"
[(return)] [(return)]
"(reload_completed "reload_completed
&& cfun->machine && cfun->machine
&& cfun->machine->is_naked)" && cfun->machine->is_naked"
"" ""
[(set_attr "cc" "none") [(set_attr "cc" "none")
(set_attr "length" "0")]) (set_attr "length" "0")])
...@@ -5805,8 +5773,7 @@ ...@@ -5805,8 +5773,7 @@
[(set (reg:QI 24) [(set (reg:QI 24)
(popcount:QI (reg:QI 24))) (popcount:QI (reg:QI 24)))
(set (reg:QI 25) (set (reg:QI 25)
(const_int 0))] (const_int 0))])
"")
;; Count Leading Zeros ;; Count Leading Zeros
...@@ -5817,9 +5784,7 @@ ...@@ -5817,9 +5784,7 @@
(clz:HI (reg:HI 24))) (clz:HI (reg:HI 24)))
(clobber (reg:QI 26))]) (clobber (reg:QI 26))])
(set (match_operand:HI 0 "register_operand" "") (set (match_operand:HI 0 "register_operand" "")
(reg:HI 24))] (reg:HI 24))])
""
"")
(define_expand "clzsi2" (define_expand "clzsi2"
[(set (reg:SI 22) [(set (reg:SI 22)
...@@ -5863,9 +5828,7 @@ ...@@ -5863,9 +5828,7 @@
(ctz:HI (reg:HI 24))) (ctz:HI (reg:HI 24)))
(clobber (reg:QI 26))]) (clobber (reg:QI 26))])
(set (match_operand:HI 0 "register_operand" "") (set (match_operand:HI 0 "register_operand" "")
(reg:HI 24))] (reg:HI 24))])
""
"")
(define_expand "ctzsi2" (define_expand "ctzsi2"
[(set (reg:SI 22) [(set (reg:SI 22)
...@@ -5911,9 +5874,7 @@ ...@@ -5911,9 +5874,7 @@
(ffs:HI (reg:HI 24))) (ffs:HI (reg:HI 24)))
(clobber (reg:QI 26))]) (clobber (reg:QI 26))])
(set (match_operand:HI 0 "register_operand" "") (set (match_operand:HI 0 "register_operand" "")
(reg:HI 24))] (reg:HI 24))])
""
"")
(define_expand "ffssi2" (define_expand "ffssi2"
[(set (reg:SI 22) [(set (reg:SI 22)
...@@ -5970,9 +5931,7 @@ ...@@ -5970,9 +5931,7 @@
(set (reg:SI 22) (set (reg:SI 22)
(bswap:SI (reg:SI 22))) (bswap:SI (reg:SI 22)))
(set (match_operand:SI 0 "register_operand" "") (set (match_operand:SI 0 "register_operand" "")
(reg:SI 22))] (reg:SI 22))])
""
"")
(define_insn "*bswapsi2.libgcc" (define_insn "*bswapsi2.libgcc"
[(set (reg:SI 22) [(set (reg:SI 22)
...@@ -6275,8 +6234,7 @@ ...@@ -6275,8 +6234,7 @@
(match_operand:QI 1 "const1_operand" "") ; width (match_operand:QI 1 "const1_operand" "") ; width
(match_operand:QI 2 "const_0_to_7_operand" "")) ; pos (match_operand:QI 2 "const_0_to_7_operand" "")) ; pos
(match_operand:QI 3 "nonmemory_operand" ""))] (match_operand:QI 3 "nonmemory_operand" ""))]
"optimize" "optimize")
"")
;; Insert bit $2.0 into $0.$1 ;; Insert bit $2.0 into $0.$1
(define_insn "*insv.reg" (define_insn "*insv.reg"
...@@ -6341,9 +6299,7 @@ ...@@ -6341,9 +6299,7 @@
[(set (match_operand:QI 0 "register_operand" "") [(set (match_operand:QI 0 "register_operand" "")
(zero_extract:QI (match_operand:QI 1 "register_operand" "") (zero_extract:QI (match_operand:QI 1 "register_operand" "")
(match_operand:QI 2 "const1_operand" "") (match_operand:QI 2 "const1_operand" "")
(match_operand:QI 3 "const_0_to_7_operand" "")))] (match_operand:QI 3 "const_0_to_7_operand" "")))])
""
"")
(define_insn "*extzv" (define_insn "*extzv"
[(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r") [(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r")
......
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