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lvzhengyang
riscv-gcc-1
Commits
47f339cf
Commit
47f339cf
authored
Sep 28, 2001
by
Bernd Schmidt
Committed by
Bernd Schmidt
Sep 28, 2001
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Add support for 3Dnow builtins
From-SVN: r45863
parent
ad919812
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Showing
7 changed files
with
89 additions
and
5 deletions
+89
-5
gcc/ChangeLog
+31
-0
gcc/c-common.c
+2
-0
gcc/config/i386/i386.c
+0
-0
gcc/config/i386/i386.h
+49
-5
gcc/config/i386/i386.md
+0
-0
gcc/tree.c
+5
-0
gcc/tree.h
+2
-0
No files found.
gcc/ChangeLog
View file @
47f339cf
2001
-
09
-
25
Bernd
Schmidt
<
bernds
@redhat
.
com
>
Mostly
from
Graham
Stott
<
grahams
@redhat
.
com
>
*
c
-
common
.
c
(
type_for_mode
)
:
Add
support
for
V2SFmode
.
*
tree
.
c
(
build_common_tree_nodes_2
)
:
Likewise
.
*
tree
.
h
(
enum
tree_index
,
global_trees
)
:
Likewise
.
*
config
/
i386
/
i386
.
c
(
x86_3dnow_a
)
:
New
variable
.
(
override_options
)
:
Support
3
Dnow
extensions
.
(
bdesc_2arg
,
bdesc_1arg
)
:
Some
SSE
instructions
are
also
part
of
Athlon
'
s
version
of
3
Dnow
.
(
ix86_init_mmx_sse_builtins
)
:
Create
3
Dnow
builtins
.
(
ix86_expand_builtin
)
:
Handle
them
.
(
ix86_hard_regno_mode_ok
)
:
Support
V2SFmode
if
using
3
Dnow
.
*
config
/
i386
/
i386
.
h
(
MASK_3DNOW
,
MASK_3DNOW_A
,
TARGET_3DNOW
,
TARGET_3DNOW_A
)
:
New
macros
.
(
TARGET_SWITCHES
)
:
Add
3
Dnow
switches
.
(
VALID_MMX_REG_MODE_3DNOW
)
:
New
macro
.
(
VECTOR_MODE_SUPPORTED_P
)
:
Use
it
.
(
enum
ix86_builtins
)
:
Add
entries
for
3
Dnow
builtins
.
*
config
/
i386
/
i386
.
md
(
movv2sf_internal
,
movv2sf
,
pushv2sf
,
pf2id
,
pf2iw
,
addv2sf3
,
subv2sf3
,
subrv2sf3
,
gtv2sf3
,
gev2sf3
,
eqv2sf3
,
pfmaxv23sf3
,
pfminv2sf3
,
mulv2sf3
,
femms
,
prefetch_3dnow
,
prefetchw
,
pfacc
,
pfnacc
,
pfpnacc
,
pi2fw
,
floatv2si2
,
pavgusb
,
pfrcpv2sf2
,
pfrcpit1v2sf3
,
pfrcpit2v2sf3
,
pfrsqrtv2sf2
,
pfrsqit1v2sf3
,
pmulhrwvhi3
,
pswapdv2si2
,
pswapdv2sf2
)
:
New
patterns
.
(
mmx_pmovmskb
,
mmx_maskmovq
,
sse_movntdi
,
umulv4hi3_highpart
,
mmx_uavgv8qi3
,
mmx_uavgv4hi3
,
mmx_psadbw
,
mmx_pinsrw
,
mmx_pextrw
,
mmx_pshufw
,
umaxv8qi3
,
smaxv4hi3
,
uminv8qi3
,
sminv4hi3
,
sfence
,
sfence_insn
,
prefetch
)
:
Make
these
available
if
TARGET_SSE
or
TARGET_3DNOW_A
.
Fri
Sep
28
19
:
18
:
40
CEST
2001
Jan
Hubicka
<
jh
@suse
.
cz
>
*
i386
-
protos
.
h
(
ix86_setup_incoming_varargs
,
ix86_va_arg
,
...
...
gcc/c-common.c
View file @
47f339cf
...
...
@@ -1347,6 +1347,8 @@ type_for_mode (mode, unsignedp)
return
V4HI_type_node
;
if
(
mode
==
TYPE_MODE
(
V8QI_type_node
)
&&
VECTOR_MODE_SUPPORTED_P
(
mode
))
return
V8QI_type_node
;
if
(
mode
==
TYPE_MODE
(
V2SF_type_node
)
&&
VECTOR_MODE_SUPPORTED_P
(
mode
))
return
V2SF_type_node
;
#endif
return
0
;
...
...
gcc/config/i386/i386.c
View file @
47f339cf
This diff is collapsed.
Click to expand it.
gcc/config/i386/i386.h
View file @
47f339cf
...
...
@@ -118,10 +118,12 @@ extern int target_flags;
#define MASK_MMX 0x00020000
/* Support MMX regs/builtins */
#define MASK_SSE 0x00040000
/* Support SSE regs/builtins */
#define MASK_SSE2 0x00080000
/* Support SSE2 regs/builtins */
#define MASK_128BIT_LONG_DOUBLE 0x00100000
/* long double size is 128bit */
#define MASK_MIX_SSE_I387 0x00200000
/* Mix SSE and i387 instructions */
#define MASK_64BIT 0x00400000
/* Produce 64bit code */
#define MASK_NO_RED_ZONE 0x00800000
/* Do not use red zone */
#define MASK_3DNOW 0x00100000
/* Support 3Dnow builtins */
#define MASK_3DNOW_A 0x00200000
/* Support Athlon 3Dnow builtins */
#define MASK_128BIT_LONG_DOUBLE 0x00400000
/* long double size is 128bit */
#define MASK_MIX_SSE_I387 0x00800000
/* Mix SSE and i387 instructions */
#define MASK_64BIT 0x01000000
/* Produce 64bit code */
#define MASK_NO_RED_ZONE 0x02000000
/* Do not use red zone */
/* Temporary codegen switches */
#define MASK_INTEL_SYNTAX 0x00000200
...
...
@@ -264,6 +266,8 @@ extern const int x86_epilogue_using_move;
#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
#define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
#define TARGET_MMX ((target_flags & MASK_MMX) != 0)
#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
...
...
@@ -335,6 +339,10 @@ extern const int x86_epilogue_using_move;
{ "mmx", MASK_MMX, N_("Support MMX builtins") }, \
{ "no-mmx", -MASK_MMX, \
N_("Do not support MMX builtins") }, \
{ "3dnow", MASK_3DNOW, \
N_("Support 3DNow! builtins") }, \
{ "no-3dnow", -MASK_3DNOW, \
N_("Do not support 3DNow! builtins") }, \
{ "sse", MASK_SSE, \
N_("Support MMX and SSE builtins and code generation") }, \
{ "no-sse", -MASK_SSE, \
...
...
@@ -918,13 +926,17 @@ extern int ix86_arch;
|| (MODE) == SFmode \
|| (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
#define VALID_MMX_REG_MODE_3DNOW(MODE) \
((MODE) == V2SFmode || (MODE) == SFmode)
#define VALID_MMX_REG_MODE(MODE) \
((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
|| (MODE) == V2SImode || (MODE) == SImode)
#define VECTOR_MODE_SUPPORTED_P(MODE) \
(VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
: VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 : 0)
: VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
: VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
#define VALID_FP_MODE_P(mode) \
((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
...
...
@@ -2204,6 +2216,38 @@ enum ix86_builtins
IX86_BUILTIN_SFENCE
,
IX86_BUILTIN_PREFETCH
,
/* 3DNow! Original */
IX86_BUILTIN_FEMMS
,
IX86_BUILTIN_PAVGUSB
,
IX86_BUILTIN_PF2ID
,
IX86_BUILTIN_PFACC
,
IX86_BUILTIN_PFADD
,
IX86_BUILTIN_PFCMPEQ
,
IX86_BUILTIN_PFCMPGE
,
IX86_BUILTIN_PFCMPGT
,
IX86_BUILTIN_PFMAX
,
IX86_BUILTIN_PFMIN
,
IX86_BUILTIN_PFMUL
,
IX86_BUILTIN_PFRCP
,
IX86_BUILTIN_PFRCPIT1
,
IX86_BUILTIN_PFRCPIT2
,
IX86_BUILTIN_PFRSQIT1
,
IX86_BUILTIN_PFRSQRT
,
IX86_BUILTIN_PFSUB
,
IX86_BUILTIN_PFSUBR
,
IX86_BUILTIN_PI2FD
,
IX86_BUILTIN_PMULHRW
,
IX86_BUILTIN_PREFETCH_3DNOW
,
/* PREFETCH already used */
IX86_BUILTIN_PREFETCHW
,
/* 3DNow! Athlon Extensions */
IX86_BUILTIN_PF2IW
,
IX86_BUILTIN_PFNACC
,
IX86_BUILTIN_PFPNACC
,
IX86_BUILTIN_PI2FW
,
IX86_BUILTIN_PSWAPDSI
,
IX86_BUILTIN_PSWAPDSF
,
/* Composite builtins, expand to more than one insn. */
IX86_BUILTIN_SETPS1
,
IX86_BUILTIN_SETPS
,
...
...
gcc/config/i386/i386.md
View file @
47f339cf
This diff is collapsed.
Click to expand it.
gcc/tree.c
View file @
47f339cf
...
...
@@ -4877,4 +4877,9 @@ build_common_tree_nodes_2 (short_double)
TREE_TYPE
(
V8QI_type_node
)
=
intQI_type_node
;
TYPE_MODE
(
V8QI_type_node
)
=
V8QImode
;
finish_vector_type
(
V8QI_type_node
);
V2SF_type_node
=
make_node
(
VECTOR_TYPE
);
TREE_TYPE
(
V2SF_type_node
)
=
float_type_node
;
TYPE_MODE
(
V2SF_type_node
)
=
V2SFmode
;
finish_vector_type
(
V2SF_type_node
);
}
gcc/tree.h
View file @
47f339cf
...
...
@@ -1846,6 +1846,7 @@ enum tree_index
TI_V8QI_TYPE
,
TI_V4HI_TYPE
,
TI_V2SI_TYPE
,
TI_V2SF_TYPE
,
TI_MAIN_IDENTIFIER
,
...
...
@@ -1911,6 +1912,7 @@ extern tree global_trees[TI_MAX];
#define V8QI_type_node global_trees[TI_V8QI_TYPE]
#define V4HI_type_node global_trees[TI_V4HI_TYPE]
#define V2SI_type_node global_trees[TI_V2SI_TYPE]
#define V2SF_type_node global_trees[TI_V2SF_TYPE]
/* An enumeration of the standard C integer types. These must be
ordered so that shorter types appear before longer ones. */
...
...
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