constraint.md (Yd, Yx): New register constraints.

	* config/i386/constraint.md (Yd, Yx): New register constraints.
	* config/i386/i386.md (*pushdf): Merge with *pushdf_nointeger.  Use
	Yd conditional register constraint.
	(*movtf_internal): Use standard_sse_constant_opcode.
	(*movxf_internal): Merge with *movxf_internal_nointeger.  Use
	Yx conditional register constraint.
	(*movdf_internal): Merge with *movdf_internal_nointeger.  Use
	Yd conditional register constraint.  Use standard_sse_constant_p to
	check for valid SSE constants and call standard_sse_constant_opcode to
	output SSE insn.
	(*movsf_internal): Use standard_sse_constant_p to check for valid SSE
	constants and call standard_sse_constant_opcode to output SSE insn.
	* config/i386/i386.c (ix86_option_ovverride_internal): Set
	TARGET_INTEGER_DFMODE_MOVES for 64bit targets.  Clear it when
	optimize_size is set.
	(standard_sse_constant_opcode): Output conditional AVX insn templates.

From-SVN: r173757

gcc/ChangeLog

+2011-05-14  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/constraint.md (Yd, Yx): New register constraints.
+	* config/i386/i386.md (*pushdf): Merge with *pushdf_nointeger.  Use
+	Yd conditional register constraint.
+	(*movtf_internal): Use standard_sse_constant_opcode.
+	(*movxf_internal): Merge with *movxf_internal_nointeger.  Use
+	Yx conditional register constraint.
+	(*movdf_internal): Merge with *movdf_internal_nointeger.  Use
+	Yd conditional register constraint.  Use standard_sse_constant_p to
+	check for valid SSE constants and call standard_sse_constant_opcode to
+	output SSE insn.
+	(*movsf_internal): Use standard_sse_constant_p to check for valid SSE
+	constants and call standard_sse_constant_opcode to output SSE insn.
+	* config/i386/i386.c (ix86_option_ovverride_internal): Set
+	TARGET_INTEGER_DFMODE_MOVES for 64bit targets.  Clear it when
+	optimize_size is set.
+	(standard_sse_constant_opcode): Output conditional AVX insn templates.
+
+2011-05-14  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/constraint.md (Yd, Yx): New register constraints.
+	* config/i386/i386.md (*pushdf): Merge with *pushdf_nointeger.  Use
+	Yd conditional register constraint.
+	(*movtf_internal): Use standard_sse_constant_opcode.
+	(*movxf_internal): Merge with *movxf_internal_nointeger.  Use
+	Yx conditional register constraint.
+	(*movdf_internal): Merge with *movdf_internal_nointeger.  Use
+	Yd conditional register constraint.  Use standard_sse_constant_p to
+	check for valid SSE constants and call standard_sse_constant_opcode to
+	output SSE insn.
+	(*movsf_internal): Use standard_sse_constant_p to check for valid SSE
+	constants and call standard_sse_constant_opcode to output SSE insn.
+	* config/i386/i386.c (ix86_option_ovverride_internal): Set
+	TARGET_INTEGER_DFMODE_MOVES for 64bit targets.  Clear it when
+	optimize_size is set.
+	(standard_sse_constant_opcode): Output conditional AVX insn templates.
+
 2011-05-14  Tobias Burnus  <burnus@net-b.de>
 
 	* doc/invoke.texi (-Ofast): Also enables -fstack-arrays.
@@ -243,11 +281,11 @@
 2011-05-11  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/i386.c (legitimize_tls_address)
-	<TLS_MODEL_GLOBAL_DYNAMIC>: Call gen_tls_dynamic_gnu2_{32,64}
+	<case TLS_MODEL_GLOBAL_DYNAMIC>: Call gen_tls_dynamic_gnu2_{32,64}
 	expanders directly for TARGET_GNU2_TLS.  Determine pic and
 	__tls_get_addr symbol reference here.  Update call to
 	gen_tls_global_dynamic_{32,64} for added arguments.
-	<TLS_MODEL_LOCAL_DYNAMIC>: Call gen_tls_dynamic_gnu2_{32,64}
+	<case TLS_MODEL_LOCAL_DYNAMIC>: Call gen_tls_dynamic_gnu2_{32,64}
 	expanders directly for TARGET_GNU2_TLS.  Determine
 	__tls_get_addr symbol reference here.  Update call to
 	gen_tls_local_dynamic_base_{32,64} for added arguments.  Attach

gcc/config/i386/constraints.md

@@ -90,6 +90,8 @@
 ;;  2	SSE2 enabled
 ;;  i	SSE2 inter-unit moves enabled
 ;;  m	MMX inter-unit moves enabled
+;;  d	Integer register when integer DFmode moves are enabled
+;;  x	Integer register when integer XFmode moves are enabled
 
 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
  "First SSE register (@code{%xmm0}).")
@@ -105,6 +107,14 @@
  "TARGET_MMX && TARGET_INTER_UNIT_MOVES ? MMX_REGS : NO_REGS"
  "@internal Any MMX register, when inter-unit moves are enabled.")
 
+(define_register_constraint "Yd"
+ "TARGET_INTEGER_DFMODE_MOVES ? GENERAL_REGS : NO_REGS"
+ "@internal Any integer register when integer DFmode moves are enabled.")
+
+(define_register_constraint "Yx"
+ "optimize_function_for_speed_p (cfun) ? GENERAL_REGS : NO_REGS"
+ "@internal Any integer register when integer XFmode moves are enabled.")
+
 ;; Integer constant constraints.
 (define_constraint "I"
   "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
@@ -149,7 +159,7 @@
 (define_constraint "G"
   "Standard 80387 floating point constant."
   (and (match_code "const_double")
-       (match_test "standard_80387_constant_p (op)")))
+       (match_test "standard_80387_constant_p (op) > 0")))
 
 ;; This can theoretically be any mode's CONST0_RTX.
 (define_constraint "C"

gcc/config/i386/i386.c

@@ -3933,6 +3933,13 @@ ix86_option_override_internal (bool main_args_p)
   if (!TARGET_80387)
     target_flags |= MASK_NO_FANCY_MATH_387;
 
+  /* On 32bit targets, avoid moving DFmode values in
+     integer registers when optimizing for size.  */
+  if (TARGET_64BIT)
+    target_flags |= TARGET_INTEGER_DFMODE_MOVES;
+  else if (optimize_size)
+    target_flags &= ~TARGET_INTEGER_DFMODE_MOVES;
+
   /* Turn on MMX builtins for -msse.  */
   if (TARGET_SSE)
     {
@@ -8580,17 +8587,17 @@ standard_sse_constant_opcode (rtx insn, rtx x)
       switch (get_attr_mode (insn))
 	{
 	case MODE_V4SF:
-	  return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
+	  return "%vxorps\t%0, %d0";
 	case MODE_V2DF:
 	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-	    return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
+	    return "%vxorps\t%0, %d0";
 	  else
-	    return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
+	    return "%vxorpd\t%0, %d0";
 	case MODE_TI:
 	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-	    return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
+	    return "%vxorps\t%0, %d0";
 	  else
-	    return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
+	    return "%vpxor\t%0, %d0";
 	case MODE_V8SF:
 	  return "vxorps\t%x0, %x0, %x0";
 	case MODE_V4DF:
@@ -8607,7 +8614,7 @@ standard_sse_constant_opcode (rtx insn, rtx x)
 	  break;
 	}
     case 2:
-      return TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" : "pcmpeqd\t%0, %0";
+      return "%vpcmpeqd\t%0, %d0";
     default:
       break;
     }