[PATCH] [Arm] Fix fpu configurations for Cortex-R7 and Cortex-R8

gcc/ChangeLog:
2018-11-29  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR target/88224
	* config/arm/arm-cpus.in (armv7-r): Add FP16conv configurations.
	(cortex-r7, cortex-r8): Update default and add new configuration.
	* doc/invoke.texi (armv7-r): Add two new vfp options.
	(nofp.dp): Add cortex-r7 and cortex-r8 to the list of targets that
	support this option.

From-SVN: r266612

gcc/ChangeLog

+2018-11-29  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	PR target/88224
+	* config/arm/arm-cpus.in (armv7-r): Add FP16conv configurations.
+	(cortex-r7, cortex-r8): Update default and add new configuration.
+	* doc/invoke.texi (armv7-r): Add two new vfp options.
+	(nofp.dp): Add cortex-r7 and cortex-r8 to the list of targets that
+	support this option.
+
 2018-11-29  Alan Modra  <amodra@gmail.com>
 
 	* config/rs6000/rs6000.c (rs6000_emit_move): Disable long

gcc/config/arm/arm-cpus.in

@@ -476,6 +476,8 @@ begin arch armv7-r
  optalias vfpv3xd fp.sp
  option fp add VFPv3 FP_DBL
  optalias vfpv3-d16 fp
+ option vfpv3xd-fp16 add VFPv3 fp16conv
+ option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv
  option idiv add adiv
  option nofp remove ALL_FP
  option noidiv remove adiv
@@ -1086,7 +1088,8 @@ end cpu cortex-r5
 begin cpu cortex-r7
  cname cortexr7
  tune flags LDSCHED
- architecture armv7-r+idiv+fp
+ architecture armv7-r+idiv+vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex
  vendor 41
@@ -1097,7 +1100,8 @@ begin cpu cortex-r8
  cname cortexr8
  tune for cortex-r7
  tune flags LDSCHED
- architecture armv7-r+idiv+fp
+ architecture armv7-r+idiv+vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex
  vendor 41

gcc/doc/invoke.texi

@@ -17090,6 +17090,14 @@ The single-precision VFPv3 floating-point instructions.  The extension
 The VFPv3 floating-point instructions with 16 double-precision registers.
 The extension +vfpv3-d16 can be used as an alias for this extension.
 
+@item +vfpv3xd-d16-fp16
+The single-precision VFPv3 floating-point instructions with 16 double-precision
+registers and the half-precision floating-point conversion operations.
+
+@item +vfpv3-d16-fp16
+The VFPv3 floating-point instructions with 16 double-precision
+registers and the half-precision floating-point conversion operations.
+
 @item +nofp
 Disable the floating-point extension.
 
@@ -17259,7 +17267,8 @@ Disables the floating-point and SIMD instructions on
 
 @item +nofp.dp
 Disables the double-precision component of the floating-point instructions
-on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}.
+on @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52} and
+@samp{cortex-m7}.
 
 @item +nosimd
 Disables the SIMD (but not floating-point) instructions on