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lvzhengyang
riscv-gcc-1
Commits
45df3663
Commit
45df3663
authored
Oct 07, 1999
by
Michael Meissner
Committed by
Michael Meissner
Oct 07, 1999
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Comment out peepholes that generate buggy code
From-SVN: r29858
parent
c2d9fa7b
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2 changed files
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27 additions
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22 deletions
+27
-22
gcc/ChangeLog
+5
-0
gcc/config/alpha/alpha.md
+22
-22
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gcc/ChangeLog
View file @
45df3663
Thu
Oct
7
15
:
23
:
28
1999
Michael
Meissner
<
meissner
@cygnus
.
com
>
*
alpha
.
md
(
peephole2
'
s
)
:
Comment
out
peephole2
'
s
that
generate
buggy
code
.
Thu
Oct
7
12
:
00
:
53
1999
Richard
Henderson
<
rth
@cygnus
.
com
>
Thu
Oct
7
12
:
00
:
53
1999
Richard
Henderson
<
rth
@cygnus
.
com
>
*
genrecog
.
c
(
add_to_sequence
)
:
Disable
mode
check
for
*
genrecog
.
c
(
add_to_sequence
)
:
Disable
mode
check
for
...
...
gcc/config/alpha/alpha.md
View file @
45df3663
...
@@ -5407,25 +5407,25 @@
...
@@ -5407,25 +5407,25 @@
;; Optimize sign-extension of SImode loads. This shows up in the wake of
;; Optimize sign-extension of SImode loads. This shows up in the wake of
;; reload when converting fp->int.
;; reload when converting fp->int.
(define_peephole2
;
(define_peephole2
[
(set (match_operand:SI 0 "register_operand" "=r")
;
[
(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "memory_operand" "m"))
;
(match_operand:SI 1 "memory_operand" "m"))
(set (match_operand:DI 2 "register_operand" "=r")
;
(set (match_operand:DI 2 "register_operand" "=r")
(sign_extend:DI (match_dup 0)))]
;
(sign_extend:DI (match_dup 0)))]
"rtx_equal_p (operands
[
0
]
, operands
[
2
]
)
;
"rtx_equal_p (operands
[
0
]
, operands
[
2
]
)
|| reg_dead_p (insn, operands
[
0
]
)"
;
|| reg_dead_p (insn, operands
[
0
]
)"
[
(set (match_dup 2)
;
[
(set (match_dup 2)
(sign_extend:DI (match_dup 1)))]
;
(sign_extend:DI (match_dup 1)))]
"")
;
"")
;
(define_peephole2
;
(define_peephole2
[
(set (match_operand:SI 0 "register_operand" "=r")
;
[
(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "hard_fp_register_operand" "f"))
;
(match_operand:SI 1 "hard_fp_register_operand" "f"))
(set (match_operand:DI 2 "register_operand" "=r")
;
(set (match_operand:DI 2 "register_operand" "=r")
(sign_extend:DI (match_dup 0)))]
;
(sign_extend:DI (match_dup 0)))]
"TARGET_FIX
;
"TARGET_FIX
&& (rtx_equal_p (operands
[
0
]
, operands
[
2
]
)
;
&& (rtx_equal_p (operands
[
0
]
, operands
[
2
]
)
|| reg_dead_p (insn, operands
[
0
]
))"
;
|| reg_dead_p (insn, operands
[
0
]
))"
[
(set (match_dup 2)
;
[
(set (match_dup 2)
(sign_extend:DI (match_dup 1)))]
;
(sign_extend:DI (match_dup 1)))]
"")
;
"")
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