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riscv-gcc-1
Commit 45c75ea7 by Kyrylo Tkachov Committed by Kyrylo Tkachov
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[ARM] Cortex-A57 rtx costs 

	* config/arm/aarch-cost-tables.h (cortexa57_extra_costs): New table.
	Remove extra newline at end of file.
	* config/arm/arm.c (arm_cortex_a57_tune): New tuning struct.
	(arm_issue_rate): Handle cortexa57.
	* config/arm/arm-cores.def (cortex-a57): Use cortex_a57 tuning.
	(cortex-a57.cortex-a53): Likewise.

From-SVN: r207565
parent 69fe2dfb
Showing with 127 additions and 3 deletions
gcc/ChangeLog
2014-02-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/aarch-cost-tables.h (cortexa57_extra_costs): New table.
Remove extra newline at end of file.
* config/arm/arm.c (arm_cortex_a57_tune): New tuning struct.
(arm_issue_rate): Handle cortexa57.
* config/arm/arm-cores.def (cortex-a57): Use cortex_a57 tuning.
(cortex-a57.cortex-a53): Likewise.
2014-02-06 Jakub Jelinek <jakub@redhat.com> 2014-02-06 Jakub Jelinek <jakub@redhat.com>
PR target/59575 PR target/59575
......
gcc/config/arm/aarch-cost-tables.h
...@@ -222,6 +222,104 @@ const struct cpu_cost_table cortexa53_extra_costs = ...@@ -222,6 +222,104 @@ const struct cpu_cost_table cortexa53_extra_costs =
} }
}; };
const struct cpu_cost_table cortexa57_extra_costs =
{
/* ALU */
{
0, /* arith. */
0, /* logical. */
0, /* shift. */
COSTS_N_INSNS (1), /* shift_reg. */
COSTS_N_INSNS (1), /* arith_shift. */
COSTS_N_INSNS (1), /* arith_shift_reg. */
COSTS_N_INSNS (1), /* log_shift. */
COSTS_N_INSNS (1), /* log_shift_reg. */
0, /* extend. */
COSTS_N_INSNS (1), /* extend_arith. */
COSTS_N_INSNS (1), /* bfi. */
0, /* bfx. */
0, /* clz. */
0, /* non_exec. */
true /* non_exec_costs_exec. */
},
{
/* MULT SImode */
{
COSTS_N_INSNS (2), /* simple. */
COSTS_N_INSNS (3), /* flag_setting. */
COSTS_N_INSNS (2), /* extend. */
COSTS_N_INSNS (2), /* add. */
COSTS_N_INSNS (2), /* extend_add. */
COSTS_N_INSNS (18) /* idiv. */
},
/* MULT DImode */
{
COSTS_N_INSNS (4), /* simple. */
0, /* flag_setting (N/A). */
COSTS_N_INSNS (2), /* extend. */
COSTS_N_INSNS (4), /* add. */
COSTS_N_INSNS (2), /* extend_add. */
COSTS_N_INSNS (34) /* idiv. */
}
},
/* LD/ST */
{
COSTS_N_INSNS (3), /* load. */
COSTS_N_INSNS (3), /* load_sign_extend. */
COSTS_N_INSNS (3), /* ldrd. */
COSTS_N_INSNS (2), /* ldm_1st. */
1, /* ldm_regs_per_insn_1st. */
2, /* ldm_regs_per_insn_subsequent. */
COSTS_N_INSNS (4), /* loadf. */
COSTS_N_INSNS (4), /* loadd. */
COSTS_N_INSNS (5), /* load_unaligned. */
0, /* store. */
0, /* strd. */
0, /* stm_1st. */
1, /* stm_regs_per_insn_1st. */
2, /* stm_regs_per_insn_subsequent. */
0, /* storef. */
0, /* stored. */
COSTS_N_INSNS (1) /* store_unaligned. */
},
{
/* FP SFmode */
{
COSTS_N_INSNS (17), /* div. */
COSTS_N_INSNS (5), /* mult. */
COSTS_N_INSNS (9), /* mult_addsub. */
COSTS_N_INSNS (9), /* fma. */
COSTS_N_INSNS (4), /* addsub. */
COSTS_N_INSNS (2), /* fpconst. */
COSTS_N_INSNS (2), /* neg. */
COSTS_N_INSNS (2), /* compare. */
COSTS_N_INSNS (4), /* widen. */
COSTS_N_INSNS (4), /* narrow. */
COSTS_N_INSNS (4), /* toint. */
COSTS_N_INSNS (4), /* fromint. */
COSTS_N_INSNS (4) /* roundint. */
},
/* FP DFmode */
{
COSTS_N_INSNS (31), /* div. */
COSTS_N_INSNS (5), /* mult. */
COSTS_N_INSNS (9), /* mult_addsub. */
COSTS_N_INSNS (9), /* fma. */
COSTS_N_INSNS (4), /* addsub. */
COSTS_N_INSNS (2), /* fpconst. */
COSTS_N_INSNS (2), /* neg. */
COSTS_N_INSNS (2), /* compare. */
COSTS_N_INSNS (4), /* widen. */
COSTS_N_INSNS (4), /* narrow. */
COSTS_N_INSNS (4), /* toint. */
COSTS_N_INSNS (4), /* fromint. */
COSTS_N_INSNS (4) /* roundint. */
}
},
/* Vector */
{
COSTS_N_INSNS (1) /* alu. */
}
};
#endif /* GCC_AARCH_COST_TABLES_H */ #endif /* GCC_AARCH_COST_TABLES_H */
gcc/config/arm/arm-cores.def
...@@ -153,7 +153,7 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, FL_LDSCHED | ...@@ -153,7 +153,7 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, FL_LDSCHED |
/* V8 Architecture Processors */ /* V8 Architecture Processors */
ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a53) ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a53)
ARM_CORE("cortex-a57", cortexa57, cortexa15, 8A, FL_LDSCHED | FL_CRC32, cortex_a15) ARM_CORE("cortex-a57", cortexa57, cortexa15, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
/* V8 big.LITTLE implementations */ /* V8 big.LITTLE implementations */
ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a15) ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
gcc/config/arm/arm.c
...@@ -1632,6 +1632,22 @@ const struct tune_params arm_cortex_a53_tune = ...@@ -1632,6 +1632,22 @@ const struct tune_params arm_cortex_a53_tune =
false /* Prefer Neon for 64-bits bitops. */ false /* Prefer Neon for 64-bits bitops. */
}; };
const struct tune_params arm_cortex_a57_tune =
{
arm_9e_rtx_costs,
&cortexa57_extra_costs,
NULL, /* Scheduler cost adjustment. */
1, /* Constant limit. */
2, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
false, /* Prefer constant pool. */
arm_default_branch_cost,
true, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
false /* Prefer Neon for 64-bits bitops. */
};
/* Branches can be dual-issued on Cortex-A5, so conditional execution is /* Branches can be dual-issued on Cortex-A5, so conditional execution is
less appealing. Set max_insns_skipped to a low value. */ less appealing. Set max_insns_skipped to a low value. */
...@@ -29352,6 +29368,7 @@ arm_issue_rate (void) ...@@ -29352,6 +29368,7 @@ arm_issue_rate (void)
switch (arm_tune) switch (arm_tune)
{ {
case cortexa15: case cortexa15:
case cortexa57:
return 3; return 3;
case cortexr4: case cortexr4:
......
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