i386: Enable MMX intrinsics without SSE/SSE2/SSSE3

Since MMX intrinsics are marked with SSE/SSE2/SSSE3 for SSE emulation,
enable them without SSE/SSE2/SSSE3 if MMX is enabled.

Restore TARGET_3DNOW check, which was changed to TARGET_3DNOW_A by
revision 271235.

gcc/

	PR target/90497
	* config/i386/i386-expand.c (ix86_expand_builtin): Enable MMX
	intrinsics without SSE/SSE2/SSSE3.
	* config/i386/mmx.md (mmx_uavgv8qi3): Restore TARGET_3DNOW
	check.
	(*mmx_uavgv8qi3): Likewise.

gcc/testsuite/

	PR target/90497
	* gcc.target/i386/pr90497-1.c: New test.
	* gcc.target/i386/pr90497-2.c: Likewise.

From-SVN: r271328

gcc/ChangeLog

+2019-05-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/90497
+	* config/i386/i386-expand.c (ix86_expand_builtin): Enable MMX
+	intrinsics without SSE/SSE2/SSSE3.
+	* config/i386/mmx.md (mmx_uavgv8qi3): Restore TARGET_3DNOW
+	check.
+	(*mmx_uavgv8qi3): Likewise.
+
 2019-05-17  Richard Biener  <rguenther@suse.de>
 
 	* gimple-pretty-print.c (dump_ternary_rhs): Handle dumping

gcc/config/i386/i386-expand.c

@@ -10937,8 +10937,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
       && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
     isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
   /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when
-     MMX is disabled.  */
-  if (TARGET_MMX_WITH_SSE)
+     MMX is disabled.  NB: Since MMX intrinsics are marked with
+     SSE/SSE2/SSSE3, enable them without SSE/SSE2/SSSE3 if MMX is
+     enabled.  */
+  if (TARGET_MMX || TARGET_MMX_WITH_SSE)
     {
       if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
 	   == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))

gcc/config/i386/mmx.md

@@ -1745,7 +1745,7 @@
 				  (const_int 1) (const_int 1)]))
 	    (const_int 1))))]
   "(TARGET_MMX || TARGET_MMX_WITH_SSE)
-   && (TARGET_SSE || TARGET_3DNOW_A)"
+   && (TARGET_SSE || TARGET_3DNOW)"
   "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
 
 (define_insn "*mmx_uavgv8qi3"
@@ -1764,7 +1764,7 @@
 				  (const_int 1) (const_int 1)]))
 	    (const_int 1))))]
   "(TARGET_MMX || TARGET_MMX_WITH_SSE)
-   && (TARGET_SSE || TARGET_3DNOW_A)
+   && (TARGET_SSE || TARGET_3DNOW)
    && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
 {
   /* These two instructions have the same operation, but their encoding

gcc/testsuite/ChangeLog

+2019-05-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/90497
+	* gcc.target/i386/pr90497-1.c: New test.
+	* gcc.target/i386/pr90497-2.c: Likewise.
+
 2019-05-17  Robin Dapp  <rdapp@linux.ibm.com>
 
 	* gcc.target/s390/global-array-element-pic.c: Add -march=z900.

gcc/testsuite/gcc.target/i386/pr90497-1.c

+/* PR target/90497 */
+/* { dg-do compile } */
+/* { dg-options "-mno-sse -mmmx" { target ia32 } } */
+/* { dg-options "-mno-mmx" { target { ! ia32 } } } */
+
+typedef char __v8qi __attribute__ ((__vector_size__ (8)));
+
+__v8qi
+foo (__v8qi x, __v8qi y)
+{
+  return __builtin_ia32_pcmpeqb (x, y);
+}

gcc/testsuite/gcc.target/i386/pr90497-2.c

+/* PR target/90497 */
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-mno-sse -m3dnow" } */
+
+typedef char __v8qi __attribute__ ((__vector_size__ (8)));
+
+__v8qi
+foo (__v8qi x, __v8qi y)
+{
+  return __builtin_ia32_pavgusb (x, y);
+}