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riscv-gcc-1
Commit 44b8152b by Ulrich Weigand Committed by Ulrich Weigand
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s390.c (s390_emit_prologue): Do not emit USE insn for GOT register; add… 

s390.c (s390_emit_prologue): Do not emit USE insn for GOT register; add REG_MAYBE_DEAD notes instead.

	* config/s390/s390.c (s390_emit_prologue): Do not emit USE
	insn for GOT register; add REG_MAYBE_DEAD notes instead.
	config/s390/s390.md (call, call_value): Add GOT register to
	CALL_INSN_FUNCTION_USAGE where needed.
	(call_exp, call_value_exp): New.

From-SVN: r48908
parent 1d6e90ac
Showing with 76 additions and 28 deletions
gcc/ChangeLog
2002-01-16 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.c (s390_emit_prologue): Do not emit USE
insn for GOT register; add REG_MAYBE_DEAD notes instead.
config/s390/s390.md (call, call_value): Add GOT register to
CALL_INSN_FUNCTION_USAGE where needed.
(call_exp, call_value_exp): New.
2002-01-16 Nick Clifton <nickc@cambridge.redhat.com>
* config/arm/arm.c: General formatting tidy up.
......
gcc/config/s390/s390.c
......@@ -2989,11 +2989,13 @@ s390_emit_prologue ()
got_symbol = force_const_mem (Pmode, got_symbol);
insn = emit_move_insn (pic_offset_table_rtx,
got_symbol);
REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
REG_NOTES (insn));
insn = emit_insn (gen_add2_insn (pic_offset_table_rtx,
gen_rtx_REG (Pmode, BASE_REGISTER)));
/* We need the GOT pointer even if we don't know it ... */
emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
REG_NOTES (insn));
}
}
}
......
gcc/config/s390/s390.md
......@@ -5965,20 +5965,14 @@
;
(define_expand "call"
[(parallel [(call (match_operand 0 "" "")
(match_operand 1 "" ""))
(clobber (match_operand 2 "" ""))])]
[(call (match_operand 0 "" "")
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))]
""
"
{
/* Abuse operand 2 to hold the return register. */
operands[2] = gen_rtx_REG (Pmode, RETURN_REGNUM);
/* In 31-bit, we must load the GOT register even if the
compiler doesn't know about it, because the PLT glue
code uses it. In 64-bit, this is not necessary. */
if (flag_pic && !TARGET_64BIT)
current_function_uses_pic_offset_table = 1;
int plt_call = 0;
rtx insn;
/* Direct function calls need special treatment. */
if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
......@@ -5987,10 +5981,12 @@
/* When calling a global routine in PIC mode, we must
replace the symbol itself with the PLT stub. */
if (flag_pic && !SYMBOL_REF_FLAG(sym))
if (flag_pic && !SYMBOL_REF_FLAG (sym))
{
sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
sym = gen_rtx_CONST (Pmode, sym);
plt_call = 1;
}
/* Unless we can use the bras(l) insn, force the
......@@ -6004,8 +6000,30 @@
operands[0] = gen_rtx_MEM (QImode, sym);
}
/* Emit insn. */
insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
gen_rtx_REG (Pmode, RETURN_REGNUM)));
/* In 31-bit, we must load the GOT register even if the
compiler doesn't know about it, because the PLT glue
code uses it. In 64-bit, this is not necessary. */
if (plt_call && !TARGET_64BIT)
{
current_function_uses_pic_offset_table = 1;
use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
}
DONE;
}")
(define_expand "call_exp"
[(parallel [(call (match_operand 0 "" "")
(match_operand 1 "" ""))
(clobber (match_operand 2 "" ""))])]
""
"")
(define_insn "brasl"
[(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
(match_operand:SI 1 "const_int_operand" "n"))
......@@ -6070,21 +6088,15 @@
;
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand 1 "" "")
(match_operand 2 "" "")))
(clobber (match_operand 3 "" ""))])]
[(set (match_operand 0 "" "")
(call (match_operand 1 "" "")
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))]
""
"
{
/* Abuse operand 3 to hold the return register. */
operands[3] = gen_rtx_REG (Pmode, RETURN_REGNUM);
/* In 31-bit, we must load the GOT register even if the
compiler doesn't know about it, because the PLT glue
code uses it. In 64-bit, this is not necessary. */
if (flag_pic && !TARGET_64BIT)
current_function_uses_pic_offset_table = 1;
int plt_call = 0;
rtx insn;
/* Direct function calls need special treatment. */
if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
......@@ -6093,10 +6105,12 @@
/* When calling a global routine in PIC mode, we must
replace the symbol itself with the PLT stub. */
if (flag_pic && !SYMBOL_REF_FLAG(sym))
if (flag_pic && !SYMBOL_REF_FLAG (sym))
{
sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
sym = gen_rtx_CONST (Pmode, sym);
plt_call = 1;
}
/* Unless we can use the bras(l) insn, force the
......@@ -6110,8 +6124,32 @@
operands[1] = gen_rtx_MEM (QImode, sym);
}
/* Emit insn. */
insn = emit_call_insn (
gen_call_value_exp (operands[0], operands[1], operands[2],
gen_rtx_REG (Pmode, RETURN_REGNUM)));
/* In 31-bit, we must load the GOT register even if the
compiler doesn't know about it, because the PLT glue
code uses it. In 64-bit, this is not necessary. */
if (plt_call && !TARGET_64BIT)
{
current_function_uses_pic_offset_table = 1;
use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
}
DONE;
}")
(define_expand "call_value_exp"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand 1 "" "")
(match_operand 2 "" "")))
(clobber (match_operand 3 "" ""))])]
""
"")
(define_insn "brasl_r"
[(set (match_operand 0 "register_operand" "=df")
(call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
......
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