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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
448ff736
Commit
448ff736
authored
Mar 14, 1992
by
Torbjorn Granlund
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*** empty log message ***
From-SVN: r473
parent
d45cf215
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gcc/config/arm/arm.md
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448ff736
...
@@ -132,12 +132,10 @@
...
@@ -132,12 +132,10 @@
;; Multiplication insns
;; Multiplication insns
;; Note the '&' in the following insn which tells GCC that the second operand
;; The `
&' is too strict, but at least generates correct code.
;; must be corruptable and hence not equal to the first. (Too strict in fact.)
(define_insn "mulsi3"
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
[
(set (match_operand:SI 0 "register_operand" "=
&
r")
(mult:SI (match_operand:SI 1 "register_operand" "
&
r")
(mult:SI (match_operand:SI 1 "register_operand" "
%
r")
(match_operand:SI 2 "register_operand" "r")))]
(match_operand:SI 2 "register_operand" "r")))]
""
""
"
*
"
*
...
@@ -150,9 +148,9 @@
...
@@ -150,9 +148,9 @@
;; Unnamed templates to match MLA instruction.
;; Unnamed templates to match MLA instruction.
(define_insn ""
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
[
(set (match_operand:SI 0 "register_operand" "=
&
r")
(plus:SI
(plus:SI
(mult:SI (match_operand:SI 1 "register_operand" "
&
r")
(mult:SI (match_operand:SI 1 "register_operand" "
%
r")
(match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 3 "register_operand" "r")))]
(match_operand:SI 3 "register_operand" "r")))]
""
""
...
@@ -164,10 +162,10 @@
...
@@ -164,10 +162,10 @@
")
")
(define_insn ""
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
[
(set (match_operand:SI 0 "register_operand" "=
&
r")
(plus:SI
(plus:SI
(match_operand:SI 3 "register_operand" "r")
(match_operand:SI 3 "register_operand" "r")
(mult:SI (match_operand:SI 1 "register_operand" "
&
r")
(mult:SI (match_operand:SI 1 "register_operand" "
%
r")
(match_operand:SI 2 "register_operand" "r"))))]
(match_operand:SI 2 "register_operand" "r"))))]
""
""
"
*
"
*
...
@@ -522,7 +520,7 @@
...
@@ -522,7 +520,7 @@
return (arm_output_asm_insn (
\"
mvfs
\\
t%0, %1
\"
, operands));
return (arm_output_asm_insn (
\"
mvfs
\\
t%0, %1
\"
, operands));
")
")
;; Zero exten
t
ion instructions.
;; Zero exten
s
ion instructions.
(define_expand "zero_extendhisi2"
(define_expand "zero_extendhisi2"
[
(set (match_operand:SI 0 "register_operand" "")
[
(set (match_operand:SI 0 "register_operand" "")
...
...
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