Commit 4470a3a3 by Uros Bizjak Committed by Uros Bizjak

i386.md (pro_epilogue_adjust_stack_<mode>_add): Merge from pro_epilogue_adjust_stack_<mode>_{1,2}.

	* config/i386/i386.md (pro_epilogue_adjust_stack_<mode>_add): Merge
	from pro_epilogue_adjust_stack_<mode>_{1,2}.
	(pro_epilogue_adjust_stack_<mode>_add): Rename from
	pro_epilogue_adjust_stack_<mode>_3.
	* config/i386/i386.c (pro_epilogue_adjust_stack): Update for
	renamed pro_epilogue_adjust_stack_{si,di}_add.
	(ix86_expand_prologue): Use indirect functions.  Update for renamed
	pro_epilogue_adjust_stack_{si,di}_sub.

From-SVN: r164635
parent d284c684
2010-09-26 Uros Bizjak <ubizjak@gmail.com> 2010-09-26 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (pro_epilogue_adjust_stack_<mode>_add): Merge
from pro_epilogue_adjust_stack_<mode>_{1,2}.
(pro_epilogue_adjust_stack_<mode>_add): Rename from
pro_epilogue_adjust_stack_<mode>_3.
* config/i386/i386.c (pro_epilogue_adjust_stack): Update for
renamed pro_epilogue_adjust_stack_{si,di}_add.
(ix86_expand_prologue): Use indirect functions. Update for renamed
pro_epilogue_adjust_stack_{si,di}_sub.
2010-09-26 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (movmsk_df): New insn. * config/i386/i386.md (movmsk_df): New insn.
(signbitdf): Split out of signbit<mode>2. Generate movmsk_df (signbitdf): Split out of signbit<mode>2. Generate movmsk_df
sequence for TARGET_SSE_MATH. sequence for TARGET_SSE_MATH.
...@@ -8777,9 +8777,11 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, ...@@ -8777,9 +8777,11 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
rtx insn; rtx insn;
if (! TARGET_64BIT) if (! TARGET_64BIT)
insn = emit_insn (gen_pro_epilogue_adjust_stack_si_1 (dest, src, offset)); insn = emit_insn (gen_pro_epilogue_adjust_stack_si_add (dest,
src, offset));
else if (x86_64_immediate_operand (offset, DImode)) else if (x86_64_immediate_operand (offset, DImode))
insn = emit_insn (gen_pro_epilogue_adjust_stack_di_1 (dest, src, offset)); insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest,
src, offset));
else else
{ {
rtx tmp; rtx tmp;
...@@ -8796,7 +8798,7 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, ...@@ -8796,7 +8798,7 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
insn = emit_insn (gen_rtx_SET (DImode, tmp, offset)); insn = emit_insn (gen_rtx_SET (DImode, tmp, offset));
if (style < 0) if (style < 0)
RTX_FRAME_RELATED_P (insn) = 1; RTX_FRAME_RELATED_P (insn) = 1;
insn = emit_insn (gen_pro_epilogue_adjust_stack_di_2 (dest, src, tmp)); insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest, src, tmp));
} }
if (style >= 0) if (style >= 0)
...@@ -9698,6 +9700,8 @@ ix86_expand_prologue (void) ...@@ -9698,6 +9700,8 @@ ix86_expand_prologue (void)
{ {
rtx eax = gen_rtx_REG (Pmode, AX_REG); rtx eax = gen_rtx_REG (Pmode, AX_REG);
rtx r10 = NULL; rtx r10 = NULL;
rtx (*adjust_stack_insn)(rtx, rtx, rtx);
bool eax_live = false; bool eax_live = false;
bool r10_live = false; bool r10_live = false;
...@@ -9722,13 +9726,12 @@ ix86_expand_prologue (void) ...@@ -9722,13 +9726,12 @@ ix86_expand_prologue (void)
emit_insn (ix86_gen_allocate_stack_worker (eax, eax)); emit_insn (ix86_gen_allocate_stack_worker (eax, eax));
/* Use the fact that AX still contains ALLOCATE. */ /* Use the fact that AX still contains ALLOCATE. */
if (TARGET_64BIT) adjust_stack_insn = (TARGET_64BIT
insn = gen_pro_epilogue_adjust_stack_di_3 (stack_pointer_rtx, ? gen_pro_epilogue_adjust_stack_di_sub
stack_pointer_rtx, eax); : gen_pro_epilogue_adjust_stack_si_sub);
else
insn = gen_pro_epilogue_adjust_stack_si_3 (stack_pointer_rtx, insn = emit_insn (adjust_stack_insn (stack_pointer_rtx,
stack_pointer_rtx, eax); stack_pointer_rtx, eax));
insn = emit_insn (insn);
if (m->fs.cfa_reg == stack_pointer_rtx) if (m->fs.cfa_reg == stack_pointer_rtx)
{ {
......
...@@ -16246,10 +16246,10 @@ ...@@ -16246,10 +16246,10 @@
;; ;;
;; in proper program order. ;; in proper program order.
(define_insn "pro_epilogue_adjust_stack_<mode>_1" (define_insn "pro_epilogue_adjust_stack_<mode>_add"
[(set (match_operand:P 0 "register_operand" "=r,r") [(set (match_operand:P 0 "register_operand" "=r,r")
(plus:P (match_operand:P 1 "register_operand" "0,r") (plus:P (match_operand:P 1 "register_operand" "0,r")
(match_operand:P 2 "<immediate_operand>" "<i>,<i>"))) (match_operand:P 2 "<nonmemory_operand>" "r<i>,l<i>")))
(clobber (reg:CC FLAGS_REG)) (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))] (clobber (mem:BLK (scratch)))]
"" ""
...@@ -16289,18 +16289,7 @@ ...@@ -16289,18 +16289,7 @@
(const_string "*"))) (const_string "*")))
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_insn "pro_epilogue_adjust_stack_<mode>_2" (define_insn "pro_epilogue_adjust_stack_<mode>_sub"
[(set (match_operand:P 0 "register_operand" "=r")
(plus:P (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "register_operand" "r")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))]
""
"add{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(define_insn "pro_epilogue_adjust_stack_<mode>_3"
[(set (match_operand:P 0 "register_operand" "=r") [(set (match_operand:P 0 "register_operand" "=r")
(minus:P (match_operand:P 1 "register_operand" "0") (minus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 2 "register_operand" "r"))) (match_operand:P 2 "register_operand" "r")))
......
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