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lvzhengyang
riscv-gcc-1
Commits
43214147
Commit
43214147
authored
Jul 29, 1995
by
Richard Kenner
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(cmpqi): Account for unsigned comparisons.
(rotrqi3, rotrhi3): Reworked. From-SVN: r10192
parent
2d1d245f
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gcc/config/1750a/1750a.md
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gcc/config/1750a/1750a.md
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43214147
;;- Machine description for GNU compiler
;;- MIL-STD-1750A version.
;; Copyright (C) 1994 Free Software Foundation, Inc.
;; Contributed by O.M.Kellogg, DASA (
okellogg@salyko.cube.net
).
;; Copyright (C) 1994
, 1995
Free Software Foundation, Inc.
;; Contributed by O.M.Kellogg, DASA (
kellogg@space.otn.dasa.de
).
;; This file is part of GNU CC.
...
...
@@ -193,12 +193,35 @@
(compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
(match_operand:QI 1 "general_operand" "I,J,i,r,m")))]
""
"@
cisp r%0,%1
cisn r%0,%J1
cim r%0,%1
cr r%0,r%1
c r%0,%1 ")
"
*
{
if (next_cc_user_is_unsigned (insn))
switch (which_alternative)
{
case 0:
case 1:
case 2:
return
\"
ucim.m %0,%1
\"
;
case 3:
return
\"
ucr.m %0,%1
\"
;
case 4:
return
\"
uc.m %0,%1
\"
;
}
else
switch (which_alternative)
{
case 0:
return
\"
cisp r%0,%1
\"
;
case 1:
return
\"
cisn r%0,%J1
\"
;
case 2:
return
\"
cim r%0,%1
\"
;
case 3:
return
\"
cr r%0,r%1
\"
;
case 4:
return
\"
c r%0,%1
\"
;
}
} ")
(define_insn "cmphi"
[
(set (cc0)
...
...
@@ -923,22 +946,18 @@
dscr r%0,r%2 ")
(define_insn "rotrqi3"
[
(set (match_operand:QI 0 "register_operand" "=r
,r
")
(rotatert:QI (match_operand:QI 1 "register_operand" "0
,0
")
(match_operand:QI 2 "
general_operand" "I,
r")))]
[
(set (match_operand:QI 0 "register_operand" "=r")
(rotatert:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "
register_operand" "
r")))]
""
"@
slc r%0,%2
neg r%2,r%2
\;
scr r%0,r%2 ")
"neg r%2,r%2
\;
scr r%0,r%2 ")
(define_insn "rotrhi3"
[
(set (match_operand:HI 0 "register_operand" "=r
,r
")
(rotatert:HI (match_operand:HI 1 "register_operand" "0
,0
")
(match_operand:QI 2 "general_operand" "
I,
r")))]
[
(set (match_operand:HI 0 "register_operand" "=r")
(rotatert:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "r")))]
""
"@
dslc r%0,%2
neg r%2,r%2
\;
dscr r%0,r%2 ")
"neg r%2,r%2
\;
dscr r%0,r%2 ")
...
...
@@ -950,7 +969,7 @@
;
********************
;; Bit field instructions, general cases.
;; "o,d" constraint causes a nonoffset
t
able memref to match the "o"
;; "o,d" constraint causes a nonoffsetable memref to match the "o"
;; so that its address is reloaded.
;; (define_insn "extv" ...
...
...
@@ -1192,7 +1211,7 @@
[
(set (pc)
(label_ref (match_operand 0 "" "")))]
""
"jc
uc
,%0")
"jc
15
,%0")
;; Call subroutine, returning value in operand 0
;; (which must be a hard register).
...
...
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