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lvzhengyang
riscv-gcc-1
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4312bb18
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4312bb18
authored
Jan 21, 2011
by
Mike Stump
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Fix typo in comment.
From-SVN: r169078
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7f9f095e
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gcc/config/arm/arm1026ejs.md
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4312bb18
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@@ -127,7 +127,7 @@
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@@ -127,7 +127,7 @@
;; output (such as umull) make their results available in two cycles;
;; output (such as umull) make their results available in two cycles;
;; the least significant word is available before the most significant
;; the least significant word is available before the most significant
;; word. That fact is not modeled; instead, the instructions are
;; word. That fact is not modeled; instead, the instructions are
;; described
.
as if the entire result was available at the end of the
;; described
as if the entire result was available at the end of the
;; cycle in which both words are available.
;; cycle in which both words are available.
;; The "umull", "umlal", "smull", and "smlal" instructions all take
;; The "umull", "umlal", "smull", and "smlal" instructions all take
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