mips.c (mips_cannot_change_mode_class): Don't check for modes smaller than 4 bytes.

gcc/
	* config/mips/mips.c (mips_cannot_change_mode_class): Don't check
	for modes smaller than 4 bytes.
	* config/mips/mips.md (*movhi_internal, *movqi_internal): Remove
	FPR alternatives.

From-SVN: r129528

gcc/ChangeLog

 2007-10-21  Richard Sandiford  <rsandifo@nildram.co.uk>
 
+	* config/mips/mips.c (mips_cannot_change_mode_class): Don't check
+	for modes smaller than 4 bytes.
+	* config/mips/mips.md (*movhi_internal, *movqi_internal): Remove
+	FPR alternatives.
+
+2007-10-21  Richard Sandiford  <rsandifo@nildram.co.uk>
+
 	* config/mips/mips-protos.h (mips_output_aligned_bss): Delete.
 	* config/mips/linux.h (BSS_SECTION_ASM_OP): Delete.
 	(ASM_OUTPUT_ALIGNED_BSS): Delete.

gcc/config/mips/mips.c

@@ -8843,14 +8843,8 @@ mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
      - If the FPU has already interpreted a value in one format, we must
        not ask it to treat the value as having a different format.
 
-     We therefore only allow changes between 4-byte and smaller integer
-     values, all of which have the "W" format as far as the FPU is
-     concerned.  */
-  return (reg_classes_intersect_p (FP_REGS, class)
-	  && (GET_MODE_CLASS (from) != MODE_INT
-	      || GET_MODE_CLASS (to) != MODE_INT
-	      || GET_MODE_SIZE (from) > 4
-	      || GET_MODE_SIZE (to) > 4));
+     We therefore disallow all mode changes involving FPRs.  */
+  return reg_classes_intersect_p (FP_REGS, class);
 }
 
 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction.  */

gcc/config/mips/mips.md

@@ -3757,8 +3757,8 @@
 })
 
 (define_insn "*movhi_internal"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*x")
-	(match_operand:HI 1 "move_operand"         "d,I,m,dJ,*f,*d,*d"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*x")
+	(match_operand:HI 1 "move_operand"         "d,I,m,dJ,*d"))]
   "!TARGET_MIPS16
    && (register_operand (operands[0], HImode)
        || reg_or_0_operand (operands[1], HImode))"
@@ -3767,12 +3767,10 @@
     li\t%0,%1
     lhu\t%0,%1
     sh\t%z1,%0
-    mfc1\t%0,%1
-    mtc1\t%1,%0
     mt%0\t%1"
-  [(set_attr "type"	"move,arith,load,store,mfc,mtc,mthilo")
+  [(set_attr "type"	"move,arith,load,store,mthilo")
    (set_attr "mode"	"HI")
-   (set_attr "length"	"4,4,*,*,4,4,4")])
+   (set_attr "length"	"4,4,*,*,4")])
 
 (define_insn "*movhi_mips16"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
@@ -3863,8 +3861,8 @@
 })
 
 (define_insn "*movqi_internal"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*x")
-	(match_operand:QI 1 "move_operand"         "d,I,m,dJ,*f,*d,*d"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*x")
+	(match_operand:QI 1 "move_operand"         "d,I,m,dJ,*d"))]
   "!TARGET_MIPS16
    && (register_operand (operands[0], QImode)
        || reg_or_0_operand (operands[1], QImode))"
@@ -3873,12 +3871,10 @@
     li\t%0,%1
     lbu\t%0,%1
     sb\t%z1,%0
-    mfc1\t%0,%1
-    mtc1\t%1,%0
     mt%0\t%1"
-  [(set_attr "type"	"move,arith,load,store,mfc,mtc,mthilo")
+  [(set_attr "type"	"move,arith,load,store,mthilo")
    (set_attr "mode"	"QI")
-   (set_attr "length"	"4,4,*,*,4,4,4")])
+   (set_attr "length"	"4,4,*,*,4")])
 
 (define_insn "*movqi_mips16"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")