Commit 42f806e5 by Alan Modra Committed by Alan Modra

re PR target/14478 ([3.3 only] rs6000 geu/ltu patterns generate incorrect code)

	PR target/14478
	* config/rs6000/rs6000.c (reg_or_neg_short_operand): Don't allow zero.

From-SVN: r82315
parent c5d2de6b
2004-05-27 Alan Modra <amodra@bigpond.net.au>
PR target/14478
* config/rs6000/rs6000.c (reg_or_neg_short_operand): Don't allow zero.
2004-05-27 Josef Zlomek <zlomekj@suse.cz> 2004-05-27 Josef Zlomek <zlomekj@suse.cz>
PR middle-end/14084 PR middle-end/14084
......
...@@ -1407,13 +1407,16 @@ reg_or_short_operand (rtx op, enum machine_mode mode) ...@@ -1407,13 +1407,16 @@ reg_or_short_operand (rtx op, enum machine_mode mode)
} }
/* Similar, except check if the negation of the constant would be /* Similar, except check if the negation of the constant would be
valid for a D-field. */ valid for a D-field. Don't allow a constant zero, since all the
patterns that call this predicate use "addic r1,r2,-constant" on
a constant value to set a carry when r2 is greater or equal to
"constant". That doesn't work for zero. */
int int
reg_or_neg_short_operand (rtx op, enum machine_mode mode) reg_or_neg_short_operand (rtx op, enum machine_mode mode)
{ {
if (GET_CODE (op) == CONST_INT) if (GET_CODE (op) == CONST_INT)
return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0;
return gpc_reg_operand (op, mode); return gpc_reg_operand (op, mode);
} }
......
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