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lvzhengyang
riscv-gcc-1
Commits
4287843d
Commit
4287843d
authored
Mar 21, 2000
by
Michael Meissner
Committed by
Michael Meissner
Mar 21, 2000
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Fix problems with -mno-fp-regs
From-SVN: r32672
parent
d0f062fb
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2 changed files
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49 additions
and
17 deletions
+49
-17
gcc/ChangeLog
+8
-0
gcc/config/alpha/alpha.md
+41
-17
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gcc/ChangeLog
View file @
4287843d
2000
-
03
-
21
Michael
Meissner
<
meissner
@redhat
.
com
>
*
config
/
alpha
/
alpha
.
md
(
floating
point
insns
)
:
Add
TARGET_FP
to
all
floating
point
insns
that
just
tested
the
macro
TARGET_HAS_XFLOATING_LIBS
.
(
movsf
/
movdf
recognizers
)
:
Add
separate
insns
if
-
mno
-
fp
-
regs
is
used
to
only
use
the
gprs
.
2000
-
03
-
21
Nathan
Sidwell
<
nathan
@codesourcery
.
com
>
2000
-
03
-
21
Nathan
Sidwell
<
nathan
@codesourcery
.
com
>
*
tree
.
h
(
COMPLETE_TYPE_P
)
:
New
macro
.
*
tree
.
h
(
COMPLETE_TYPE_P
)
:
New
macro
.
...
...
gcc/config/alpha/alpha.md
View file @
4287843d
...
@@ -2093,7 +2093,7 @@
...
@@ -2093,7 +2093,7 @@
(define_expand "fix_trunctfdi2"
(define_expand "fix_trunctfdi2"
[
(use (match_operand:DI 0 "register_operand" ""))
[
(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))]
(use (match_operand:TF 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FIX, operands); DONE;")
"alpha_emit_xfloating_cvt (FIX, operands); DONE;")
(define_insn ""
(define_insn ""
...
@@ -2131,25 +2131,25 @@
...
@@ -2131,25 +2131,25 @@
(define_expand "floatditf2"
(define_expand "floatditf2"
[
(use (match_operand:TF 0 "register_operand" ""))
[
(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:DI 1 "general_operand" ""))]
(use (match_operand:DI 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
"alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
(define_expand "floatunsdisf2"
(define_expand "floatunsdisf2"
[
(use (match_operand:SF 0 "register_operand" ""))
[
(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:DI 1 "register_operand" ""))]
(use (match_operand:DI 1 "register_operand" ""))]
""
"
TARGET_FP
"
"alpha_emit_floatuns (operands); DONE;")
"alpha_emit_floatuns (operands); DONE;")
(define_expand "floatunsdidf2"
(define_expand "floatunsdidf2"
[
(use (match_operand:DF 0 "register_operand" ""))
[
(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DI 1 "register_operand" ""))]
(use (match_operand:DI 1 "register_operand" ""))]
""
"
TARGET_FP
"
"alpha_emit_floatuns (operands); DONE;")
"alpha_emit_floatuns (operands); DONE;")
(define_expand "floatunsditf2"
(define_expand "floatunsditf2"
[
(use (match_operand:TF 0 "register_operand" ""))
[
(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:DI 1 "general_operand" ""))]
(use (match_operand:DI 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
"alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
(define_expand "extendsfdf2"
(define_expand "extendsfdf2"
...
@@ -2183,7 +2183,7 @@
...
@@ -2183,7 +2183,7 @@
(define_expand "extendsftf2"
(define_expand "extendsftf2"
[
(use (match_operand:TF 0 "register_operand" ""))
[
(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:SF 1 "general_operand" ""))]
(use (match_operand:SF 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"
"
{
{
rtx tmp = gen_reg_rtx (DFmode);
rtx tmp = gen_reg_rtx (DFmode);
...
@@ -2195,7 +2195,7 @@
...
@@ -2195,7 +2195,7 @@
(define_expand "extenddftf2"
(define_expand "extenddftf2"
[
(use (match_operand:TF 0 "register_operand" ""))
[
(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:DF 1 "general_operand" ""))]
(use (match_operand:DF 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
"alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
(define_insn ""
(define_insn ""
...
@@ -2217,13 +2217,13 @@
...
@@ -2217,13 +2217,13 @@
(define_expand "trunctfdf2"
(define_expand "trunctfdf2"
[
(use (match_operand:DF 0 "register_operand" ""))
[
(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))]
(use (match_operand:TF 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
"alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
(define_expand "trunctfsf2"
(define_expand "trunctfsf2"
[
(use (match_operand:SF 0 "register_operand" ""))
[
(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))]
(use (match_operand:TF 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"
"
{
{
rtx tmpf, sticky, arg, lo, hi;
rtx tmpf, sticky, arg, lo, hi;
...
@@ -2317,7 +2317,7 @@
...
@@ -2317,7 +2317,7 @@
[
(use (match_operand 0 "register_operand" ""))
[
(use (match_operand 0 "register_operand" ""))
(use (match_operand 1 "general_operand" ""))
(use (match_operand 1 "general_operand" ""))
(use (match_operand 2 "general_operand" ""))]
(use (match_operand 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (DIV, operands); DONE;")
"alpha_emit_xfloating_arith (DIV, operands); DONE;")
(define_insn ""
(define_insn ""
...
@@ -2381,7 +2381,7 @@
...
@@ -2381,7 +2381,7 @@
[
(use (match_operand 0 "register_operand" ""))
[
(use (match_operand 0 "register_operand" ""))
(use (match_operand 1 "general_operand" ""))
(use (match_operand 1 "general_operand" ""))
(use (match_operand 2 "general_operand" ""))]
(use (match_operand 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (MULT, operands); DONE;")
"alpha_emit_xfloating_arith (MULT, operands); DONE;")
(define_insn ""
(define_insn ""
...
@@ -2455,7 +2455,7 @@
...
@@ -2455,7 +2455,7 @@
[
(use (match_operand 0 "register_operand" ""))
[
(use (match_operand 0 "register_operand" ""))
(use (match_operand 1 "general_operand" ""))
(use (match_operand 1 "general_operand" ""))
(use (match_operand 2 "general_operand" ""))]
(use (match_operand 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (MINUS, operands); DONE;")
"alpha_emit_xfloating_arith (MINUS, operands); DONE;")
(define_insn ""
(define_insn ""
...
@@ -3172,7 +3172,7 @@
...
@@ -3172,7 +3172,7 @@
(define_expand "cmptf"
(define_expand "cmptf"
[
(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
[
(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
(match_operand:TF 1 "general_operand" "")))]
(match_operand:TF 1 "general_operand" "")))]
"TARGET_HAS_XFLOATING_LIBS"
"TARGET_
FP && TARGET_
HAS_XFLOATING_LIBS"
"
"
{
{
alpha_compare.op0 = operands
[
0
]
;
alpha_compare.op0 = operands
[
0
]
;
...
@@ -4209,7 +4209,7 @@
...
@@ -4209,7 +4209,7 @@
(define_insn ""
(define_insn ""
[
(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,
*r,*
r,m,m")
[
(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,
*r,*
r,m,m")
(match_operand:SF 1 "input_operand" "fG,m,
*rG,m,fG,*
r"))]
(match_operand:SF 1 "input_operand" "fG,m,
*rG,m,fG,*
r"))]
"! TARGET_FIX
"
TARGET_FPREGS &&
! TARGET_FIX
&& (register_operand (operands
[
0
]
, SFmode)
&& (register_operand (operands
[
0
]
, SFmode)
|| reg_or_fp0_operand (operands
[
1
]
, SFmode))"
|| reg_or_fp0_operand (operands
[
1
]
, SFmode))"
"@
"@
...
@@ -4224,7 +4224,7 @@
...
@@ -4224,7 +4224,7 @@
(define_insn ""
(define_insn ""
[
(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,
*r,*
r,m,m,f,
*
r")
[
(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,
*r,*
r,m,m,f,
*
r")
(match_operand:SF 1 "input_operand" "fG,m,
*rG,m,fG,*
r,
*
r,f"))]
(match_operand:SF 1 "input_operand" "fG,m,
*rG,m,fG,*
r,
*
r,f"))]
"TARGET_FIX
"TARGET_F
PREGS && TARGET_F
IX
&& (register_operand (operands
[
0
]
, SFmode)
&& (register_operand (operands
[
0
]
, SFmode)
|| reg_or_fp0_operand (operands
[
1
]
, SFmode))"
|| reg_or_fp0_operand (operands
[
1
]
, SFmode))"
"@
"@
...
@@ -4239,9 +4239,21 @@
...
@@ -4239,9 +4239,21 @@
[
(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
]
)
[
(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
]
)
(define_insn ""
(define_insn ""
[
(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
(match_operand:SF 1 "input_operand" "rG,m,r"))]
"! TARGET_FPREGS
&& (register_operand (operands
[
0
]
, SFmode)
|| reg_or_fp0_operand (operands
[
1
]
, SFmode))"
"@
mov %r1,%0
ldl %0,%1
stl %r1,%0"
[
(set_attr "type" "ilog,ild,ist")
]
)
(define_insn ""
[
(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,
*r,*
r,m,m")
[
(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,
*r,*
r,m,m")
(match_operand:DF 1 "input_operand" "fG,m,
*rG,m,fG,*
r"))]
(match_operand:DF 1 "input_operand" "fG,m,
*rG,m,fG,*
r"))]
"! TARGET_FIX
"
TARGET_FPREGS &&
! TARGET_FIX
&& (register_operand (operands
[
0
]
, DFmode)
&& (register_operand (operands
[
0
]
, DFmode)
|| reg_or_fp0_operand (operands
[
1
]
, DFmode))"
|| reg_or_fp0_operand (operands
[
1
]
, DFmode))"
"@
"@
...
@@ -4256,7 +4268,7 @@
...
@@ -4256,7 +4268,7 @@
(define_insn ""
(define_insn ""
[
(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,
*r,*
r,m,m,f,
*
r")
[
(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,
*r,*
r,m,m,f,
*
r")
(match_operand:DF 1 "input_operand" "fG,m,
*rG,m,fG,*
r,
*
r,f"))]
(match_operand:DF 1 "input_operand" "fG,m,
*rG,m,fG,*
r,
*
r,f"))]
"TARGET_FIX
"TARGET_F
PREGS && TARGET_F
IX
&& (register_operand (operands
[
0
]
, DFmode)
&& (register_operand (operands
[
0
]
, DFmode)
|| reg_or_fp0_operand (operands
[
1
]
, DFmode))"
|| reg_or_fp0_operand (operands
[
1
]
, DFmode))"
"@
"@
...
@@ -4270,6 +4282,18 @@
...
@@ -4270,6 +4282,18 @@
ftoit %1,%0"
ftoit %1,%0"
[
(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
]
)
[
(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
]
)
(define_insn ""
[
(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
(match_operand:DF 1 "input_operand" "rG,m,r"))]
"! TARGET_FPREGS
&& (register_operand (operands
[
0
]
, DFmode)
|| reg_or_fp0_operand (operands
[
1
]
, DFmode))"
"@
mov %r1,%0
ldq %0,%1
stq %r1,%0"
[
(set_attr "type" "ilog,ild,ist")
]
)
;; Subregs suck for register allocation. Pretend we can move TFmode
;; Subregs suck for register allocation. Pretend we can move TFmode
;; data between general registers until after reload.
;; data between general registers until after reload.
(define_insn ""
(define_insn ""
...
...
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