Commit 425c08a1 by Jeffrey A Law Committed by Jeff Law

calls.c (expand_call): Use bitfield instructions to extract/deposit word sized hunks when...

        * calls.c (expand_call): Use bitfield instructions to extract/deposit
        word sized hunks when loading unaligned args into registers.

From-SVN: r22008
parent cc1f7752
...@@ -14,6 +14,9 @@ Wed Aug 26 09:30:59 1998 Nick Clifton <nickc@cygnus.com> ...@@ -14,6 +14,9 @@ Wed Aug 26 09:30:59 1998 Nick Clifton <nickc@cygnus.com>
Wed Aug 26 12:57:09 1998 Jeffrey A Law (law@cygnus.com) Wed Aug 26 12:57:09 1998 Jeffrey A Law (law@cygnus.com)
* calls.c (expand_call): Use bitfield instructions to extract/deposit
word sized hunks when loading unaligned args into registers.
* haifa-sched.c (sched_analyze_insn): Only create scheduling * haifa-sched.c (sched_analyze_insn): Only create scheduling
barriers for LOOP, EH and SETJMP notes on the loop_notes list. barriers for LOOP, EH and SETJMP notes on the loop_notes list.
......
...@@ -1800,16 +1800,16 @@ expand_call (exp, target, ignore) ...@@ -1800,16 +1800,16 @@ expand_call (exp, target, ignore)
{ {
rtx reg = gen_reg_rtx (word_mode); rtx reg = gen_reg_rtx (word_mode);
rtx word = operand_subword_force (args[i].value, j, BLKmode); rtx word = operand_subword_force (args[i].value, j, BLKmode);
int bitsize = TYPE_ALIGN (TREE_TYPE (args[i].tree_value)); int bitsize = MIN (bytes * BITS_PER_UNIT, BITS_PER_WORD);
int bitpos; int bitalign = TYPE_ALIGN (TREE_TYPE (args[i].tree_value));
args[i].aligned_regs[j] = reg; args[i].aligned_regs[j] = reg;
/* Clobber REG and move each partword into it. Ensure we don't /* There is no need to restrict this code to loading items
go past the end of the structure. Note that the loop below in TYPE_ALIGN sized hunks. The bitfield instructions can
works because we've already verified that padding load up entire word sized registers efficiently.
and endianness are compatible.
??? This may not be needed anymore.
We use to emit a clobber here but that doesn't let later We use to emit a clobber here but that doesn't let later
passes optimize the instructions we emit. By storing 0 into passes optimize the instructions we emit. By storing 0 into
the register later passes know the first AND to zero out the the register later passes know the first AND to zero out the
...@@ -1818,20 +1818,14 @@ expand_call (exp, target, ignore) ...@@ -1818,20 +1818,14 @@ expand_call (exp, target, ignore)
emit_move_insn (reg, const0_rtx); emit_move_insn (reg, const0_rtx);
for (bitpos = 0; bytes -= bitsize / BITS_PER_UNIT;
bitpos < BITS_PER_WORD && bytes > 0; store_bit_field (reg, bitsize, big_endian_correction, word_mode,
bitpos += bitsize, bytes -= bitsize / BITS_PER_UNIT) extract_bit_field (word, bitsize, 0, 1,
{ NULL_RTX, word_mode,
int xbitpos = bitpos + big_endian_correction; word_mode,
bitalign / BITS_PER_UNIT,
store_bit_field (reg, bitsize, xbitpos, word_mode, BITS_PER_WORD),
extract_bit_field (word, bitsize, bitpos, 1, bitalign / BITS_PER_UNIT, BITS_PER_WORD);
NULL_RTX, word_mode,
word_mode,
bitsize / BITS_PER_UNIT,
BITS_PER_WORD),
bitsize / BITS_PER_UNIT, BITS_PER_WORD);
}
} }
} }
......
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