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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
41a38208
Commit
41a38208
authored
Dec 27, 2016
by
Uros Bizjak
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* ChangeLog: Update my last entry.
From-SVN: r243946
parent
1b5d6ccd
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41a38208
2016-12-27 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (ix86_secondary_reload): Require QImode
intermediate for mask register spill only for !TARGET_AVX512DQ.
intermediate for
QImode
mask register spill only for !TARGET_AVX512DQ.
Always use true_regnum to determine operand regno.
2016-12-27 Sandra Loosemore <sandra@codesourcery.com>
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