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Commit 41453183 by Claudiu Zissulescu Committed by Claudiu Zissulescu
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[ARC] Automatic context save/restore for regular interrupts. 

The AUX_IRQ_CTRL register controls the behavior of automated register
save and restore or prologue and epilogue sequences during a non-fast
interrupt entry and exit, and context save and restore instructions.

A user passes to the compiler the configuration of the AUX_IRQ_CTRL
register via mirq-ctrl-saved option.  This option, specifies
gneral-purposes registers that the processor saves/restores on
interrupt entry and exit, and it is only valid for ARC EM and ARC HS
cores.

gcc/
2017-05-09  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (irq_ctrl_saved): New variable.
	(ARC_AUTOBLINK_IRQ_P): Define.
	(ARC_AUTOFP_IRQ_P): Likewise.
	(ARC_AUTO_IRQ_P): Likewise.
	(irq_range): New function.
	(arc_must_save_register): Likewise.
	(arc_must_save_return_addr): Likewise.
	(arc_dwarf_emit_irq_save_regs): Likewise.
	(arc_override_options): Handle deferred options.
	(MUST_SAVE_REGISTER): Deleted, replaced by arc_must_save_register.
	(MUST_SAVE_RETURN_ADDR): Deleted, replaced by
	arc_must_save_return_addr.
	(arc_compute_frame_size): Handle automated save and restore of
	registers.
	(arc_expand_prologue): Likewise.
	(arc_expand_epilogue): Likewise.
	* config/arc/arc.md (stack_irq_dwarf): New unspec instruction.
	* config/arc/arc.opt (mirq-ctrl-saved): New option.
	* doc/invoke.texi (mirq-ctrl-saved): Document option.

testsuite/
2017-05-09  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/interrupt-5.c: Newfile.
	* gcc.target/arc/interrupt-6.c: Likewise.
	* gcc.target/arc/interrupt-7.c: Likewise.
	* gcc.target/arc/interrupt-8.c: Likewise.
	* gcc.target/arc/interrupt-9.c: Likewise.

From-SVN: r247795
parent 019bd543
Showing with 153 additions and 1 deletions
ChangeLog
2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (irq_ctrl_saved): New variable.
(ARC_AUTOBLINK_IRQ_P): Define.
(ARC_AUTOFP_IRQ_P): Likewise.
(ARC_AUTO_IRQ_P): Likewise.
(irq_range): New function.
(arc_must_save_register): Likewise.
(arc_must_save_return_addr): Likewise.
(arc_dwarf_emit_irq_save_regs): Likewise.
(arc_override_options): Handle deferred options.
(MUST_SAVE_REGISTER): Deleted, replaced by arc_must_save_register.
(MUST_SAVE_RETURN_ADDR): Deleted, replaced by
arc_must_save_return_addr.
(arc_compute_frame_size): Handle automated save and restore of
registers.
(arc_expand_prologue): Likewise.
(arc_expand_epilogue): Likewise.
* config/arc/arc.md (stack_irq_dwarf): New unspec instruction.
* config/arc/arc.opt (mirq-ctrl-saved): New option.
* doc/invoke.texi (mirq-ctrl-saved): Document option.
2017-04-19 Thomas Koenig <tkoenig@gcc.gnu.org>
Tobias Burnus <tobias.burnus@physik.fu-berlin.de>
......
gcc/config/arc/arc.md
......@@ -6241,6 +6241,14 @@
[(set (zero_extract:SI (match_dup 3) (match_dup 1) (match_dup 2))
(zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)))])
;; Dummy pattern used as a place holder for automatically saved
;; registers.
(define_insn "stack_irq_dwarf"
[(unspec_volatile [(const_int 1)] VUNSPEC_ARC_STACK_IRQ)]
""
""
[(set_attr "length" "0")])
;; include the arc-FPX instructions
(include "fpx.md")
......
gcc/config/arc/arc.opt
......@@ -486,3 +486,7 @@ Enable use of NPS400 xld/xst extension.
munaligned-access
Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
Enable unaligned word and halfword accesses to packed data.
mirq-ctrl-saved=
Target RejectNegative Joined Var(arc_deferred_options) Defer
Specifies the registers that the processor saves on an interrupt entry and exit.
gcc/doc/invoke.texi
......@@ -606,7 +606,7 @@ Objective-C and Objective-C++ Dialects}.
-mnorm -mspfp -mspfp-compact -mspfp-fast -msimd -msoft-float -mswap @gol
-mcrc -mdsp-packa -mdvbf -mlock -mmac-d16 -mmac-24 -mrtsc -mswape @gol
-mtelephony -mxy -misize -mannotate-align -marclinux -marclinux_prof @gol
-mlong-calls -mmedium-calls -msdata @gol
-mlong-calls -mmedium-calls -msdata -mirq-ctrl-saved @gol
-mvolatile-cache -mtp-regno=@var{regno} @gol
-malign-call -mauto-modify-reg -mbbit-peephole -mno-brcc @gol
-mcase-vector-pcrel -mcompact-casesi -mno-cond-exec -mearly-cbranchsi @gol
......@@ -14547,6 +14547,15 @@ hardware extensions. Not available for ARC EM@.
@end table
@item -mirq-ctrl-saved=@var{register-range}, @var{blink}, @var{lp_count}
@opindex mirq-ctrl-saved
Specifies general-purposes registers that the processor automatically
saves/restores on interrupt entry and exit. @var{register-range} is
specified as two registers separated by a dash. The register range
always starts with @code{r0}, the upper limit is @code{fp} register.
@var{blink} and @var{lp_count} are optional. This option is only
valid for ARC EM and ARC HS cores.
@end table
The following options are passed through to the assembler, and also
......
gcc/testsuite/ChangeLog
2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/interrupt-5.c: Newfile.
* gcc.target/arc/interrupt-6.c: Likewise.
* gcc.target/arc/interrupt-7.c: Likewise.
* gcc.target/arc/interrupt-8.c: Likewise.
* gcc.target/arc/interrupt-9.c: Likewise.
2017-05-09 Richard Biener <rguenther@suse.de>
* gcc.dg/vect/vect-44.c: Add --param vect-max-peeling-for-alignment=0
......
gcc/testsuite/gcc.target/arc/interrupt-5.c 0 → 100644
/* { dg-do compile } */
/* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */
/* { dg-options "-O2 -mirq-ctrl-saved=r0-r3,blink" } */
/* Check if the registers R0-R3,blink are automatically saved. */
extern int bar (void *);
void __attribute__ ((interrupt("ilink")))
foo(void)
{
bar (0);
__asm__ volatile ( "" : : : "r0","r1","r2","r3");
}
/* { dg-final { scan-assembler-not "st.*r0,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r1,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r2,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r3,\\\[sp" } } */
/* { dg-final { scan-assembler-not "push_s blink" } } */
gcc/testsuite/gcc.target/arc/interrupt-6.c 0 → 100644
/* { dg-do compile } */
/* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */
/* { dg-options "-O2 -mirq-ctrl-saved=r0-ilink" } */
#include <alloca.h>
/* Check if ilink is recognized. Check how FP and BLINK are saved.
BLINK is saved last on the stack because the IRQ autosave will do
first r0-ilink. To avoid this ABI exception, one needs to autosave
always blink when using the IRQ autosave feature. */
extern int bar (void *);
void __attribute__ ((interrupt("ilink")))
foo(void)
{
int *p = alloca (10);
bar (p);
}
/* { dg-final { scan-assembler-not ".*fp,\\\[sp" } } */
/* { dg-final { scan-assembler "ld.*blink,\\\[sp\\\]" } } */
/* { dg-final { scan-assembler "push_s.*blink" } } */
gcc/testsuite/gcc.target/arc/interrupt-7.c 0 → 100644
/* { dg-do compile } */
/* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */
/* { dg-options "-O2 -mirq-ctrl-saved=r0-r17,blink" } */
/* Check if the registers R0-R17,blink are automatically saved. */
void __attribute__ ((interrupt("ilink")))
foo(void)
{
__asm__ volatile ( "" : : : "r13","r14","r15","r16");
}
/* { dg-final { scan-assembler-not "st.*r13,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r14,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r15,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r16,\\\[sp" } } */
/* { dg-final { scan-assembler-not "push_s blink" } } */
gcc/testsuite/gcc.target/arc/interrupt-8.c 0 → 100644
/* { dg-do compile } */
/* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */
/* { dg-options "-O2 -mirq-ctrl-saved=r0-r17" } */
/* Check if the registers R0-R17 are automatically saved. GP is saved
by the compiler. */
int a;
void __attribute__ ((interrupt("ilink")))
foo(void)
{
__asm__ volatile ( "" : : : "r0","r1","r2","r3");
__asm__ volatile ( "" : : : "r13","r14","r15","r16");
a++;
}
/* { dg-final { scan-assembler-not "st.*r13,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r14,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r15,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r16,\\\[sp" } } */
/* { dg-final { scan-assembler "st.*gp,\\\[sp,-4\\\]" } } */
/* { dg-final { scan-assembler "ld.*gp,\\\[sp\\\]" } } */
/* { dg-final { scan-assembler-not "st.*r0,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r1,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r2,\\\[sp" } } */
/* { dg-final { scan-assembler-not "st.*r3,\\\[sp" } } */
/* { dg-final { scan-assembler "rtie" } } */
gcc/testsuite/gcc.target/arc/interrupt-9.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target archs }*/
/* { dg-options "-O0 -mirq-ctrl-saved=r0-fp" } */
/* Check if we get the move operation between fp and sp. */
void __attribute__ ((interrupt("ilink")))
handler1 (void)
{
asm (""
:
:
: "r0", "r1", "r2", "r3", "r4",
"r5", "r6", "r7", "r8", "r9");
}
/* { dg-final { scan-assembler "mov.*fp,sp" } } */
/* { dg-final { scan-assembler-not ".*fp,\\\[sp" } } */
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