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riscv-gcc-1
Commit 40b80dad by Richard Henderson Committed by Richard Henderson
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alpha.c (reg_not_elim_operand): New. 

        * alpha.c (reg_not_elim_operand): New.
        * alpha.h (PREDICATE_CODES): Add it.
        * alpha.md (s48addq, s48subq patterns): Use it as the predicate
        for the multiplicand.

From-SVN: r23650
parent 06ca2010
Showing with 51 additions and 108 deletions
gcc/ChangeLog
Fri Nov 13 22:19:23 1998 Richard Henderson <rth@cygnus.com>
* alpha.c (reg_not_elim_operand): New.
* alpha.h (PREDICATE_CODES): Add it.
* alpha.md (s48addq, s48subq patterns): Use it as the predicate
for the multiplicand.
Fri Nov 13 22:50:37 1998 David Edelsohn <edelsohn@mhpcc.edu> Fri Nov 13 22:50:37 1998 David Edelsohn <edelsohn@mhpcc.edu>
* rs6000.md (movsf): Remove explicit secondary-reload-like * rs6000.md (movsf): Remove explicit secondary-reload-like
......
gcc/config/alpha/alpha.c
...@@ -833,6 +833,31 @@ any_memory_operand (op, mode) ...@@ -833,6 +833,31 @@ any_memory_operand (op, mode)
&& REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER)); && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
} }
/* Returns 1 if OP is not an eliminable register.
This exists to cure a pathological abort in the s8addq (et al) patterns,
long foo () { long t; bar(); return (long) &t * 26107; }
which run afoul of a hack in reload to cure a (presumably) similar
problem with lea-type instructions on other targets. But there is
one of us and many of them, so work around the problem by selectively
preventing combine from making the optimization. */
int
reg_not_elim_operand (op, mode)
register rtx op;
enum machine_mode mode;
{
rtx inner = op;
if (GET_CODE (op) == SUBREG)
inner = SUBREG_REG (op);
if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
return 0;
return register_operand (op, mode);
}
/* Return 1 if this function can directly return via $26. */ /* Return 1 if this function can directly return via $26. */
int int
......
gcc/config/alpha/alpha.h
...@@ -2293,7 +2293,8 @@ do { \ ...@@ -2293,7 +2293,8 @@ do { \
{"unaligned_memory_operand", {MEM}}, \ {"unaligned_memory_operand", {MEM}}, \
{"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \ {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
{"any_memory_operand", {MEM}}, \ {"any_memory_operand", {MEM}}, \
{"hard_fp_register_operand", {SUBREG, REG}}, {"hard_fp_register_operand", {SUBREG, REG}}, \
{"reg_not_elim_operand", {SUBREG, REG}},
/* Tell collect that the object format is ECOFF. */ /* Tell collect that the object format is ECOFF. */
#define OBJECT_FORMAT_COFF #define OBJECT_FORMAT_COFF
...@@ -2484,6 +2485,7 @@ extern int divmod_operator (); ...@@ -2484,6 +2485,7 @@ extern int divmod_operator ();
extern int call_operand (); extern int call_operand ();
extern int reg_or_cint_operand (); extern int reg_or_cint_operand ();
extern int hard_fp_register_operand (); extern int hard_fp_register_operand ();
extern int reg_not_elim_operand ();
extern void alpha_set_memflags (); extern void alpha_set_memflags ();
extern int aligned_memory_operand (); extern int aligned_memory_operand ();
extern void get_aligned_mem (); extern void get_aligned_mem ();
......
gcc/config/alpha/alpha.md
...@@ -484,7 +484,7 @@ ...@@ -484,7 +484,7 @@
(sign_extend:DI (sign_extend:DI
(plus:SI (match_operand:SI 1 "register_operand" "") (plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))) (match_operand:SI 2 "const_int_operand" ""))))
(clobber (match_operand:SI 3 "register_operand" ""))] (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
"! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) % 4 == 0" && INTVAL (operands[2]) % 4 == 0"
[(set (match_dup 3) (match_dup 4)) [(set (match_dup 3) (match_dup 4))
...@@ -554,24 +554,24 @@ ...@@ -554,24 +554,24 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ") (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
(match_operand:SI 2 "const48_operand" "I,I")) (match_operand:SI 2 "const48_operand" "I,I"))
(match_operand:SI 3 "sext_add_operand" "rI,O")))] (match_operand:SI 3 "sext_add_operand" "rI,O")))]
"" ""
"@ "@
s%2addl %r1,%3,%0 s%2addl %1,%3,%0
s%2subl %r1,%n3,%0") s%2subl %1,%n3,%0")
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r") [(set (match_operand:DI 0 "register_operand" "=r,r")
(sign_extend:DI (sign_extend:DI
(plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ") (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
(match_operand:SI 2 "const48_operand" "I,I")) (match_operand:SI 2 "const48_operand" "I,I"))
(match_operand:SI 3 "sext_add_operand" "rI,O"))))] (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
"" ""
"@ "@
s%2addl %r1,%3,%0 s%2addl %1,%3,%0
s%2subl %r1,%n3,%0") s%2subl %1,%n3,%0")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -581,7 +581,7 @@ ...@@ -581,7 +581,7 @@
(match_operand 3 "" "")]) (match_operand 3 "" "")])
(match_operand:SI 4 "const48_operand" "")) (match_operand:SI 4 "const48_operand" ""))
(match_operand:SI 5 "add_operand" "")))) (match_operand:SI 5 "add_operand" ""))))
(clobber (match_operand:DI 6 "register_operand" ""))] (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
"" ""
[(set (match_dup 6) (match_dup 7)) [(set (match_dup 6) (match_dup 7))
(set (match_dup 0) (set (match_dup 0)
...@@ -596,105 +596,14 @@ ...@@ -596,105 +596,14 @@
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r") [(set (match_operand:DI 0 "register_operand" "=r,r")
(plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
(match_operand:DI 2 "const48_operand" "I,I")) (match_operand:DI 2 "const48_operand" "I,I"))
(match_operand:DI 3 "sext_add_operand" "rI,O")))] (match_operand:DI 3 "sext_add_operand" "rI,O")))]
"" ""
"@ "@
s%2addq %r1,%3,%0 s%2addq %1,%3,%0
s%2subq %1,%n3,%0") s%2subq %1,%n3,%0")
;; These variants of the above insns can occur if the third operand
;; is the frame pointer. This is a kludge, but there doesn't
;; seem to be a way around it. Only recognize them while reloading.
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=&r")
(plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
(match_operand:DI 2 "some_operand" "r"))
(match_operand:DI 3 "some_operand" "rIOKL")))]
"reload_in_progress"
"#")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" ""))
(match_operand:DI 3 "add_operand" "")))]
"reload_completed"
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:SI 0 "some_operand" "=&r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
(match_operand:SI 2 "const48_operand" "I"))
(match_operand:SI 3 "some_operand" "r"))
(match_operand:SI 4 "some_operand" "rIOKL")))]
"reload_in_progress"
"#")
(define_split
[(set (match_operand:SI 0 "register_operand" "r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
(match_operand:SI 3 "register_operand" ""))
(match_operand:SI 4 "add_operand" "rIOKL")))]
"reload_completed"
[(set (match_dup 0)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
"")
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=&r")
(sign_extend:DI
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "some_operand" "rJ")
(match_operand:SI 2 "const48_operand" "I"))
(match_operand:SI 3 "some_operand" "r"))
(match_operand:SI 4 "some_operand" "rIOKL"))))]
"reload_in_progress"
"#")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
(match_operand:SI 3 "register_operand" ""))
(match_operand:SI 4 "add_operand" ""))))]
"reload_completed"
[(set (match_dup 5)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
"
{ operands[5] = gen_lowpart (SImode, operands[0]);
}")
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=&r")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
(match_operand:DI 2 "const48_operand" "I"))
(match_operand:DI 3 "some_operand" "r"))
(match_operand:DI 4 "some_operand" "rIOKL")))]
"reload_in_progress"
"#")
(define_split
[(set (match_operand:DI 0 "register_operand" "=")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "const48_operand" ""))
(match_operand:DI 3 "register_operand" ""))
(match_operand:DI 4 "add_operand" "")))]
"reload_completed"
[(set (match_dup 0)
(plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
"")
(define_insn "negsi2" (define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
...@@ -758,28 +667,28 @@ ...@@ -758,28 +667,28 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
(match_operand:SI 2 "const48_operand" "I")) (match_operand:SI 2 "const48_operand" "I"))
(match_operand:SI 3 "reg_or_8bit_operand" "rI")))] (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
"" ""
"s%2subl %r1,%3,%0") "s%2subl %1,%3,%0")
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (sign_extend:DI
(minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
(match_operand:SI 2 "const48_operand" "I")) (match_operand:SI 2 "const48_operand" "I"))
(match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
"" ""
"s%2subl %r1,%3,%0") "s%2subl %1,%3,%0")
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
(match_operand:DI 2 "const48_operand" "I")) (match_operand:DI 2 "const48_operand" "I"))
(match_operand:DI 3 "reg_or_8bit_operand" "rI")))] (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
"" ""
"s%2subq %r1,%3,%0") "s%2subq %1,%3,%0")
(define_insn "mulsi3" (define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
......
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