Commit 40858b9d by Wilco Dijkstra Committed by Wilco Dijkstra

[ARM] Simplify logical DImode iterators

Further simplify the logical DImode expander using code iterator and
obtab attributes.  This avoids adding unnecessary code_attr entries.

    gcc/
	* config/arm/arm.md (<logical_op>di3): Use <optab> and <CODE>.
	* config/arm/iterators.md (optab): Add and, ior, xor entries.
	(logical_op): Remove code attribute.
	(logical_OP): Likewise.

From-SVN: r275970
parent 9f576d30
2019-09-19 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.md (<logical_op>di3): Use <optab> and <CODE>.
* config/arm/iterators.md (optab): Add and, ior, xor entries.
(logical_op): Remove code attribute.
(logical_OP): Likewise.
2019-09-19 Martin Liska <mliska@suse.cz> 2019-09-19 Martin Liska <mliska@suse.cz>
* ipa-icf.c (sort_congruence_class_groups_by_decl_uid): * ipa-icf.c (sort_congruence_class_groups_by_decl_uid):
......
...@@ -2039,16 +2039,16 @@ ...@@ -2039,16 +2039,16 @@
; operands or complex immediates, which leads to fewer LDRD/STRD instructions. ; operands or complex immediates, which leads to fewer LDRD/STRD instructions.
; So an explicit expander is needed to generate better code. ; So an explicit expander is needed to generate better code.
(define_expand "<logical_op>di3" (define_expand "<LOGICAL:optab>di3"
[(set (match_operand:DI 0 "s_register_operand") [(set (match_operand:DI 0 "s_register_operand")
(LOGICAL:DI (match_operand:DI 1 "s_register_operand") (LOGICAL:DI (match_operand:DI 1 "s_register_operand")
(match_operand:DI 2 "arm_<logical_op>di_operand")))] (match_operand:DI 2 "arm_<optab>di_operand")))]
"TARGET_32BIT" "TARGET_32BIT"
{ {
rtx low = simplify_gen_binary (<logical_OP>, SImode, rtx low = simplify_gen_binary (<CODE>, SImode,
gen_lowpart (SImode, operands[1]), gen_lowpart (SImode, operands[1]),
gen_lowpart (SImode, operands[2])); gen_lowpart (SImode, operands[2]));
rtx high = simplify_gen_binary (<logical_OP>, SImode, rtx high = simplify_gen_binary (<CODE>, SImode,
gen_highpart (SImode, operands[1]), gen_highpart (SImode, operands[1]),
gen_highpart_mode (SImode, DImode, gen_highpart_mode (SImode, DImode,
operands[2])); operands[2]));
......
...@@ -287,9 +287,6 @@ ...@@ -287,9 +287,6 @@
(define_code_attr vfml_op [(plus "a") (minus "s")]) (define_code_attr vfml_op [(plus "a") (minus "s")])
(define_code_attr logical_op [(ior "ior") (xor "xor") (and "and")])
(define_code_attr logical_OP [(ior "IOR") (xor "XOR") (and "AND")])
;;---------------------------------------------------------------------------- ;;----------------------------------------------------------------------------
;; Int iterators ;; Int iterators
;;---------------------------------------------------------------------------- ;;----------------------------------------------------------------------------
...@@ -797,7 +794,14 @@ ...@@ -797,7 +794,14 @@
(umax "u")]) (umax "u")])
(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) (define_code_attr cnb [(ltu "CC_C") (geu "CC")])
(define_code_attr optab [(ltu "ltu") (geu "geu")])
;; Map rtl operator codes to optab names
(define_code_attr optab
[(ltu "ltu")
(geu "geu")
(and "and")
(ior "ior")
(xor "xor")])
;; Assembler mnemonics for signedness of widening operations. ;; Assembler mnemonics for signedness of widening operations.
(define_code_attr US [(sign_extend "s") (zero_extend "u")]) (define_code_attr US [(sign_extend "s") (zero_extend "u")])
......
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