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lvzhengyang
riscv-gcc-1
Commits
3fbbd9e5
Commit
3fbbd9e5
authored
Apr 05, 2018
by
Chung-Ju Wu
Committed by
Chung-Ju Wu
Apr 05, 2018
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[NDS32] Refine negsi2 pattern.
gcc/ * config/nds32/nds32.md (negsi2): Refine pattern. From-SVN: r259118
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gcc/ChangeLog
View file @
3fbbd9e5
2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/nds32.md (negsi2): Refine pattern.
2018-04-05 Kito Cheng <kito.cheng@gmail.com>
2018-04-05 Kito Cheng <kito.cheng@gmail.com>
Chung-Ju Wu <jasonwucj@gmail.com>
Chung-Ju Wu <jasonwucj@gmail.com>
...
...
gcc/config/nds32/nds32.md
View file @
3fbbd9e5
...
@@ -773,15 +773,15 @@
...
@@ -773,15 +773,15 @@
;; And for V2 ISA, there is NO 'neg33' instruction.
;; And for V2 ISA, there is NO 'neg33' instruction.
;; The only option is to use 'subri A,B,0' (its semantic is 'A = 0 - B').
;; The only option is to use 'subri A,B,0' (its semantic is 'A = 0 - B').
(define_insn "negsi2"
(define_insn "negsi2"
[
(set (match_operand:SI 0 "register_operand" "=
w
, r")
[
(set (match_operand:SI 0 "register_operand" "=
l
, r")
(neg:SI (match_operand:SI 1 "register_operand" "
w
, r")))]
(neg:SI (match_operand:SI 1 "register_operand" "
l
, r")))]
""
""
"@
"@
neg33
\t
%0, %1
neg33
\t
%0, %1
subri
\t
%0, %1, 0"
subri
\t
%0, %1, 0"
[
(set_attr "type" "alu,alu")
[
(set_attr "type"
"alu,alu")
(set_attr "length"
" 2, 4")]
)
(set_attr "length"
" 2, 4"
)
(set_attr "feature" "v3m, v1")])
;; ----------------------------------------------------------------------------
;; ----------------------------------------------------------------------------
;; 'ONE_COMPLIMENT' operation
;; 'ONE_COMPLIMENT' operation
...
...
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