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Commit 3f4d9b98 by Paul Brook
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vfp.md: Move pipeline description for VFP11 to... 

2008-08-26  Paul Brook   <paul@codesourcery.com>

	* config/arm/vfp.md: Move pipeline description for VFP11 to...
	* config/arm/vfp11.md: ...here.  New.
	* config/arm/arm.md: Include vfp11.md.

From-SVN: r139599
parent 4e9b57fa
Showing with 97 additions and 83 deletions
gcc/config/arm/arm.md
...@@ -351,6 +351,7 @@ ...@@ -351,6 +351,7 @@
(include "arm1136jfs.md") (include "arm1136jfs.md")
(include "cortex-a8.md") (include "cortex-a8.md")
(include "cortex-r4.md") (include "cortex-r4.md")
(include "vfp11.md")
;;--------------------------------------------------------------------------- ;;---------------------------------------------------------------------------
......
gcc/config/arm/vfp.md
;; ARM VFP coprocessor Machine Description ;; ARM VFP instruction patterns
;; Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. ;; Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
;; Written by CodeSourcery, LLC. ;; Written by CodeSourcery.
;; ;;
;; This file is part of GCC. ;; This file is part of GCC.
;; ;;
...@@ -23,41 +23,6 @@ ...@@ -23,41 +23,6 @@
[(VFPCC_REGNUM 127)] [(VFPCC_REGNUM 127)]
) )
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Pipeline description
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_automaton "vfp11")
;; There are 3 pipelines in the VFP11 unit.
;;
;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
;; fourth stage for simple operations.
;;
;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
;; These insns also uses first execute stage of FMAC pipeline.
;;
;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
;; second memory stage for loads.
;; We do not model Write-After-Read hazards.
;; We do not do write scheduling with the arm core, so it is only necessary
;; to model the first stage of each pipeline
;; ??? Need to model LS pipeline properly for load/store multiple?
;; We do not model fmstat properly. This could be done by modeling pipelines
;; properly and defining an absence set between a dummy fmstat unit and all
;; other vfp units.
(define_cpu_unit "fmac" "vfp11")
(define_cpu_unit "ds" "vfp11")
(define_cpu_unit "vfp_ls" "vfp11")
(define_cpu_unit "fmstat" "vfp11")
(exclusion_set "fmac,ds" "fmstat")
;; The VFP "type" attributes differ from those used in the FPA model. ;; The VFP "type" attributes differ from those used in the FPA model.
;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp. ;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp.
;; farith Most arithmetic insns. ;; farith Most arithmetic insns.
...@@ -71,51 +36,6 @@ ...@@ -71,51 +36,6 @@
;; r_2_f Transfer arm to vfp reg. ;; r_2_f Transfer arm to vfp reg.
;; f_cvt Convert floating<->integral ;; f_cvt Convert floating<->integral
(define_insn_reservation "vfp_ffarith" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "ffarith"))
"fmac")
(define_insn_reservation "vfp_farith" 8
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "farith,f_cvt"))
"fmac")
(define_insn_reservation "vfp_fmul" 9
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fmul"))
"fmac*2")
(define_insn_reservation "vfp_fdivs" 19
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fdivs"))
"ds*15")
(define_insn_reservation "vfp_fdivd" 33
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fdivd"))
"fmac+ds*29")
;; Moves to/from arm regs also use the load/store pipeline.
(define_insn_reservation "vfp_fload" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_loads,f_loadd,r_2_f"))
"vfp_ls")
(define_insn_reservation "vfp_fstore" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_stores,f_stored,f_2_r"))
"vfp_ls")
(define_insn_reservation "vfp_to_cpsr" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_flag"))
"fmstat,vfp_ls*3")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Insn pattern
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; SImode moves ;; SImode moves
;; ??? For now do not allow loading constants into vfp regs. This causes ;; ??? For now do not allow loading constants into vfp regs. This causes
;; problems because small constants get converted into adds. ;; problems because small constants get converted into adds.
......
gcc/config/arm/vfp11.md 0 → 100644
;; ARM VFP11 pipeline description
;; Copyright (C) 2003, 2005, 2007, 2008 Free Software Foundation, Inc.
;; Written by CodeSourcery.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to the Free
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
;; 02110-1301, USA. */
(define_automaton "vfp11")
;; There are 3 pipelines in the VFP11 unit.
;;
;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
;; fourth stage for simple operations.
;;
;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
;; These insns also uses first execute stage of FMAC pipeline.
;;
;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
;; second memory stage for loads.
;; We do not model Write-After-Read hazards.
;; We do not do write scheduling with the arm core, so it is only necessary
;; to model the first stage of each pipeline
;; ??? Need to model LS pipeline properly for load/store multiple?
;; We do not model fmstat properly. This could be done by modeling pipelines
;; properly and defining an absence set between a dummy fmstat unit and all
;; other vfp units.
(define_cpu_unit "fmac" "vfp11")
(define_cpu_unit "ds" "vfp11")
(define_cpu_unit "vfp_ls" "vfp11")
(define_cpu_unit "fmstat" "vfp11")
(exclusion_set "fmac,ds" "fmstat")
(define_insn_reservation "vfp_ffarith" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "ffarith"))
"fmac")
(define_insn_reservation "vfp_farith" 8
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "farith,f_cvt"))
"fmac")
(define_insn_reservation "vfp_fmul" 9
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fmul"))
"fmac*2")
(define_insn_reservation "vfp_fdivs" 19
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fdivs"))
"ds*15")
(define_insn_reservation "vfp_fdivd" 33
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fdivd"))
"fmac+ds*29")
;; Moves to/from arm regs also use the load/store pipeline.
(define_insn_reservation "vfp_fload" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_loads,f_loadd,r_2_f"))
"vfp_ls")
(define_insn_reservation "vfp_fstore" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_stores,f_stored,f_2_r"))
"vfp_ls")
(define_insn_reservation "vfp_to_cpsr" 4
(and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "f_flag"))
"fmstat,vfp_ls*3")
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