[ARC] Deprecate mexpand-adddi option.

Emitting subregs in the expand will result in broken code due to LRA handling of them. Issue observed while turning on mlra and mexpand-adddi options using dejagnu test suite. Deprecate this
option.

gcc/
2017-04-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (adddi3): Remove support for mexpand-adddi
	option.
	(subdi3): Likewise.
	* config/arc/arc.opt (mexpand-adddi): Deprecate it.
	* doc/invoke.texi (mexpand-adddi): Update text.

From-SVN: r250276

gcc/ChangeLog

 2017-07-17  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* config/arc/arc.md (adddi3): Remove support for mexpand-adddi
+	option.
+	(subdi3): Likewise.
+	* config/arc/arc.opt (mexpand-adddi): Deprecate it.
+	* doc/invoke.texi (mexpand-adddi): Update text.
+
+2017-07-17  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* config/arc/arc.md (clzsi2): Expand to an arc_clzsi2 instruction
 	that also clobbers the CC register. The old expand code is moved
 	to ...

gcc/config/arc/arc.md

@@ -2649,30 +2649,7 @@
 			    (match_operand:DI 2 "nonmemory_operand" "")))
 	      (clobber (reg:CC CC_REG))])]
   ""
-{
-  if (TARGET_EXPAND_ADDDI)
-    {
-      rtx l0 = gen_lowpart (SImode, operands[0]);
-      rtx h0 = disi_highpart (operands[0]);
-      rtx l1 = gen_lowpart (SImode, operands[1]);
-      rtx h1 = disi_highpart (operands[1]);
-      rtx l2 = gen_lowpart (SImode, operands[2]);
-      rtx h2 = disi_highpart (operands[2]);
-      rtx cc_c = gen_rtx_REG (CC_Cmode, CC_REG);
-
-      if (CONST_INT_P (h2) && INTVAL (h2) < 0 && SIGNED_INT12 (INTVAL (h2)))
-	{
-	  emit_insn (gen_sub_f (l0, l1, gen_int_mode (-INTVAL (l2), SImode)));
-	  emit_insn (gen_sbc (h0, h1,
-			      gen_int_mode (-INTVAL (h2) - (l1 != 0), SImode),
-			      cc_c));
-	  DONE;
-	}
-      emit_insn (gen_add_f (l0, l1, l2));
-      emit_insn (gen_adc (h0, h1, h2));
-      DONE;
-    }
-})
+{})
 
 ; This assumes that there can be no strictly partial overlap between
 ; operands[1] and operands[2].
@@ -2911,20 +2888,6 @@
 {
   if (!register_operand (operands[2], DImode))
     operands[1] = force_reg (DImode, operands[1]);
-  if (TARGET_EXPAND_ADDDI)
-    {
-      rtx l0 = gen_lowpart (SImode, operands[0]);
-      rtx h0 = disi_highpart (operands[0]);
-      rtx l1 = gen_lowpart (SImode, operands[1]);
-      rtx h1 = disi_highpart (operands[1]);
-      rtx l2 = gen_lowpart (SImode, operands[2]);
-      rtx h2 = disi_highpart (operands[2]);
-      rtx cc_c = gen_rtx_REG (CC_Cmode, CC_REG);
-
-      emit_insn (gen_sub_f (l0, l1, l2));
-      emit_insn (gen_sbc (h0, h1, h2, cc_c));
-      DONE;
-    }
 })
 
 (define_insn_and_split "subdi3_i"

gcc/config/arc/arc.opt

@@ -328,7 +328,7 @@ Target Var(TARGET_Q_CLASS)
 Enable 'q' instruction alternatives.
 
 mexpand-adddi
-Target Var(TARGET_EXPAND_ADDDI)
+Target Warn(%qs is deprecated)
 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 
 

gcc/doc/invoke.texi

@@ -14906,7 +14906,7 @@ Enable pre-reload use of the @code{cbranchsi} pattern.
 @item -mexpand-adddi
 @opindex mexpand-adddi
 Expand @code{adddi3} and @code{subdi3} at RTL generation time into
-@code{add.f}, @code{adc} etc.
+@code{add.f}, @code{adc} etc.  This option is deprecated.
 
 @item -mindexed-loads
 @opindex mindexed-loads